Flash memory structure and method of manufacture

• US 6,255,689 B1
• Filed: 12/20/1999
• Issued: 07/03/2001
• Est. Priority Date: 12/20/1999
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Robin
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/467,251
• Time in Patent Office: 561 Days
• Field of Search: 257/314, 257/315, 257/316, 257/513, 438/201, 438/221, 438/209, 438/212, 438/230, 438/694
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.

Claims

1. A method of manufacturing a flash memory, comprising the steps of:

providing a substrate having a patterned mask layer thereon;

transferring a pattern of the patterned mask layer to the substrate so that an opening is formed in the substrate;

forming a first liner oxide layer over an exposed substrate inside the opening;

forming spacers on sidewalls of the opening, wherein the each spacer has a first base width;

forming a trench in the substrate at a bottom of the opening while using the patterned mask layer and the spacers as a hard mask;

forming an insulation layer in the trench to form a shallow trench isolation structure;

reducing the first base width of the spacers to a second base width;

removing the patterned mask layer;

forming a first doped region in the substrate next to an upper corner of the insulation layer and a second doped region in the substrate under the patterned mask layer, wherein the first doped region serves as a source terminal and the second doped region serves as a drain terminal;

removing the spacers;

forming an etching stop layer over the second doped region;

forming a tunnel oxide layer over the substrate between the first and the second doped region;

forming conductive spacers over the tunnel oxide coated sidewalls between the first and the second doped region;

forming a first dielectric layer over the conductive spacers;

forming a conductive layer inside the opening above the first dielectric layer; and

patterning the conductive layer, the first dielectric layer and the conductive spacers to form a plurality of control gates, a plurality of second dielectric layers and a plurality of floating gates, respectively.

2. The method of claim 1, wherein the step of forming the spacers includes depositing silicon nitride.

3. The method of claim 1, wherein after the step of forming the first and the second doped region, further includes forming a third doped region in the substrate under the second doped region next to the first doped region and a fourth doped region in the substrate under the shallow trench isolation structure.

4. The method of claim 3, wherein ions used for forming the first and the second doped region have a polarity opposite to the ions used for forming the third and the fourth doped region.

5. The method of claim 1, wherein before the step of forming the first and the second doped region, further includes forming a third doped region in the substrate under the second doped region next to the first doped region and a fourth doped region in the substrate under the shallow trench isolation structure.

6. The method of claim 5, wherein ions used for forming the first and the second ped region have a polarity opposite to that of the ions used for forming the third and the fourth doped region.

7. The method of claim 1, wherein the step of forming the conductive spacers includes depositing doped polysilicon.

8. The method of claim 1, wherein the step of forming the conductive layer includes depositing doped polysilicon.

9. The method of claim 1, wherein the step of forming the first dielectric layer includes depositing silicon oxide.

10. A flash memory cell structure, comprising:

a substrate having a protruding section and a recessed section, wherein the protruding section has a sidewall and there is a substrate surface between the protruding section and the recessed section;

a tunnel oxide layer over the substrate surface between the protruding section and the recessed section;

a common drain terminal at a top end of the protruding section;

a source terminal located in the substrate between the protruding section and the recessed section;

a floating gate above the tunnel oxide and between the source terminal and the drain terminal;

a dielectric layer above the floating gate;

a shallow trench isolation structure in the recessed section; and

a control gate between the dielectric layer and the shallow trench isolation structure.

11. The structure of claim 10, wherein a material for forming the floating gate includes doped polysilicon.

12. The structure of claim 10, wherein a material for forming the control gate includes doped polysilicon.

13. The structure of claim 10, wherein a material for forming the first dielectric layer includes silicon oxide.