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TFT CMOS logic circuit having source/drain electrodes of differing spacing from the gate electrode for decreasing wiring capacitance and power consumption

  • US 6,255,695 B1
  • Filed: 09/18/1997
  • Issued: 07/03/2001
  • Est. Priority Date: 09/20/1996
  • Status: Expired due to Term
First Claim
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1. A semiconductor device comprising:

  • an n-channel field effect transistor and a p-channel field effect transistor both disposed over a substrate, each of said n-channel and p-channel field effect transistors comprising;

    a source region, a drain region, and a channel forming region disposed between the source and drain regions;

    a gate electrode disposed adjacent to the channel forming region through a gate insulating film; and

    a source electrode connected to the source region, wherein said n-channel and p-channel field effect transistors constitute an inverter circuit having an input terminal and an output terminal and a common drain electrode, wherein said gate electrode of said n-channel field effect transistor is connected with said gate electrode of said p-channel field effect transistor, and said input terminal is connected with both of said gate electrodes of said n-channel and p-channel field effect transistors, wherein said common drain electrode is connected to the drain regions of said n-channel and p-channel field effect transistors, and said output terminal is connected to said common drain electrode, wherein in at least one of the n-channel and p-channel field-effect transistors, a distance between the gate electrode and the common drain electrode is longer than a distance between the gate electrode and the source electrode, wherein said source electrode connected to the source region of said n-channel field effect transistor is connected to a ground potential, and wherein said source electrode connected to the source region of said p-channel field effect transistor is connected to a power supply line.

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