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Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit

  • US 6,255,698 B1
  • Filed: 04/28/1999
  • Issued: 07/03/2001
  • Est. Priority Date: 04/28/1999
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region;

    an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor in direct contact with a first gate dielectric, and wherein said first rate conductor comprises a low-temperature metal; and

    a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a low-temperature metal, and wherein a composition of said second gate structure is different than a composition of said first gate structure.

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