Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit

• US 6,255,698 B1
• Filed: 04/28/1999
• Issued: 07/03/2001
• Est. Priority Date: 04/28/1999
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Fulford, H. Jim Jr.
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US09/301,263
• Time in Patent Office: 797 Days
• Field of Search: 257/368, 257/369, 257/371, 257/374, 257/388, 257/409, 257/410, 257/411, 257/412
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).

Claims

1. An integrated circuit, comprising:

an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region;

an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor in direct contact with a first gate dielectric, and wherein said first rate conductor comprises a low-temperature metal; and

a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a low-temperature metal, and wherein a composition of said second gate structure is different than a composition of said first gate structure.

2. The integrated circuit as recited in claim 1, wherein a dielectric constant of said first gate dielectric is larger than a dielectric constant of said second gate dielectric.

3. The integrated circuit as recited in claim 1, wherein said second gate conductor comprises a diffusion barrier layer.

4. The integrated circuit as recited in claim 3, wherein said diffusion barrier layer comprises a metal nitride.

5. The integrated circuit as recited in claim 4, wherein said metal nitride comprises titanium nitride.

6. The integrated circuit as recited in claim 1, wherein a thickness of said first gate dielectric is smaller than a thickness of said second gate dielectric.

7. The integrated circuit as recited in claim 1, wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.

8. The integrated circuit as recited in claim 1, wherein said low-temperature metal comprises aluminum, an aluminum alloy, copper, or a copper alloy.

9. The integrated circuit as recited in claim 1, wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.

10. An integrated circuit, comprising:

an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region;

an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate structure comprises a first gate conductor over a first gate dielectric; and

a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein said second gate structure comprises a second gate conductor over a second gate dielectric, and wherein said second gate conductor comprises a diffusion barrier layer interposed between said second gate conductor and said second gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure, and wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.

11. The integrated circuit as recited in claim 10, wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.

12. The integrated circuit as recited in claim 10, wherein a dielectric constant of said first gate dielectric is larger than a dielectric constant of said second gate dielectric.

13. The integrated circuit as recited in claim 10, wherein said first and said second gate conductors consist essentially of metal.

14. An integrated circuit, comprising:

an n-type active region of a semiconductor substrate separated from a p-type active region of said substrate by an isolation region;

an n-channel transistor comprising a first gate structure arranged above said p-type active region, wherein said first gate conductor comprises a first gate conductor over a first gate dielectric; and

a p-channel transistor comprising a second gate structure arranged above said n-type active region, wherein second gate structure comprises a second gate conductor over a second gate dielectric, and wherein a dielectric constant of said second gate dielectric is smaller than a dielectric constant of said first gate dielectric, and wherein a composition of said second gate structure is different than a composition of said first gate structure.

15. The integrated circuit as recited in claim 14, wherein a work function of said first gate conductor is different than a work function of said second gate conductor, such that a magnitude of a threshold voltage of said p-channel transistor is approximately equal to a magnitude of a threshold voltage of said n-channel transistor.

16. The integrated circuit as recited in claim 14, wherein said first and said second gate conductors consist essentially of metal.

17. The integrated circuit as recited in claim 14, wherein said second gate conductor comprises a diffusion barrier layer.

18. The integrated circuit as recited in claim 14, wherein a lateral length of said first gate structure is smaller than a lateral length of said second gate structure.