Semiconductor device and method for fabricating the same

• US 6,255,704 B1
• Filed: 06/24/1997
• Issued: 07/03/2001
• Est. Priority Date: 06/28/1996
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Iwata, Hiroshi, Nakano, Masayuki, Matsuoka, Toshimasa, Kakimoto, Seizou
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/881,697
• Time in Patent Office: 1,470 Days
• Field of Search: 257/368, 257/369, 257/371, 257/520, 257/401
• US Class Current: 257/401
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein the gate electrode includes a polycrystalline silicon film formed on the gate insulating film and metal silicide film formed on the polycrystalline silicon film, and

wherein the metal silicide film is electrically connected to a corresponding one of the one or more shallow well regions via the contact region of the corresponding one of the one or more shallow well regions,

a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the one or more shallow well regions is diffused at a higher concentration than that of a reminder of the one or more shallow well regions, is formed in the contact region, and

an Ohmic contact is formed between the metal silicide film and the corresponding one of the one or more shallow well regions through the high concentration impurity diffusion region.

2. A semiconductor device according to claim 1, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

3. A semiconductor device according to claim 1, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation regions which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

4. A semiconductor device according to claim 1, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

5. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

the semiconductor device further comprising an interlayer insulating film and an upper wiring provided on the interlayer insulating film,

wherein a contact hole is formed in the interlayer insulating film, which penetrates through the gate electrode and the gate insulating film so as to reach the contact region of the one corresponding one of the one or more shallow well regions,

wherein a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the one or more shallow well regions is diffused at a higher concentration than that of a remainder of the one or more shallow well regions, is formed in the contact region,

an Ohmic contact is formed between the upper wiring and the one or more shallow well regions through the high concentration impurity diffusion region on the bottom of the contact hole, and

wherein an Ohmic contact is formed between the gate electrode and the upper wiring on a side wall region of the contact hole.

6. A semiconductor device according to claim 5, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

7. A semiconductor device according to claim 5, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

8. A semiconductor device according to claim 5, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

9. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein a difference of a potential formed between the one or more shallow well regions and the source region and a difference of a potential formed between the one or more shallow well regions and the drain region are set so as to be smaller than a built-in potential for a pn junction formed between the source/drain regions of the first conductivity type and the one or more shallow well regions of the second conductivity type during operation.

10. A semiconductor device according to claim 9, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

11. A semiconductor device according to claim 9, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

12. A semiconductor device according to claim 9, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

13. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein the gate electrode is electrically connected to the corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and a constant voltage is applied to a gate electrode of the second MOS transistor.

14. A semiconductor device according to claim 13, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

15. A semiconductor device according to claim 13, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

16. A semiconductor device according to claim 13, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

17. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein the gate electrode is electrically connected to the corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and the drain region is connected to a second gate electrode of the second MOS transistor.

18. A semiconductor device according to claim 17, wherein adjacent shallow well regions are separated form each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

19. A semiconductor device according to claim 17, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

20. A semiconductor device according to claim 17, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

21. A semiconductor device comprising:

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein a pn junction portion, which is formed between at least bottoms of the source/drain regions of the first conductivity type and the one or more shallow well regions of the second conductivity type, contains carbon bonded to silicon or nitrogen bonded to silicon, and

a built-in potential of the pn junction portion, formed between at least the bottoms of the source/drain regions of the first conductivity type and the one or more shallow well regions of the second conductivity type, is set so as to be higher than a built-in potential of pn junction formed of a p-type silicon and an n-type silicon.

22. A semiconductor device according to claim 21, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

23. A semiconductor device according to claim 21, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent source and/or drain regions from each other.

24. A semiconductor device according to claim 21, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

25. A semiconductor device comprising a first block circuit or a second block circuit or both of the first and the second block circuits, wherein:

the first block circuit is positioned between a circuit block constituted by using a further semiconductor device and a power supply voltage source; and

the second block circuit is positioned between the circuit block and a ground voltage supply source,

wherein the further semiconductor device comprises;

a semiconductor substrate;

a deep well region of a first conductivity type, formed in the semiconductor substrate;

one or more shallow well regions of a second conductivity type, formed in the deep well region;

a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions;

a channel region formed between the source region and the drain region;

a gate insulating film formed on the channel region; and

a gate electrode formed on the gate insulating film,

wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and

the one or more shallow well regions is electrically separated from one or more adjacent shallow well regions,

wherein supply of a power supply voltage or supply of a ground voltage or both of the supply of the power supply voltage and the supply of the voltage are blocked when the circuit block is in a standby state.

26. A semiconductor device according to claim 25, wherein adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the one or more shallow well regions and shallower than the deep well region.

27. A semiconductor device according to claim 25, further comprising:

a groove type of first element separation region which electrically separates adjacent shallow well regions from each other, and

a second element separation region which has a thickness greater than that of the gate insulating film and electrically separates the adjacent and/or drain regions from each other.

28. A semiconductor device according to claim 25, wherein the deep well region of the first conductivity type is capable of functioning as an emitter or a collector of a bipolar transistor;

the one or more shallow well regions of the second conductivity type are capable of functioning as a base of the bipolar transistor;

the source region and the drain region of the first conductivity type are capable of functioning as the collector or the emitter of the bipolar transistor;

wherein the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.

29. A semiconductor device comprising:

a semiconductor substrate;

an n-type deep well region formed in the semiconductor substrate;

a p-type deep well region formed in the semiconductor substrate;

a p-type shallow well region formed in the n-type deep well region;

an n-type shallow well region formed in the p-type deep well region;

an N-channel MOS transistor formed in the p-type shallow well region; and

a P-channel MOS transistor formed in the n-type shallow well region,

wherein the N-channel MOS transistor includes an n-type source region and an n-type drain region formed in the p-type shallow well region, a channel region formed between the n-type source region and the n-type drain region, a gate insulating film formed on the channel region, and an n-type gate electrode formed on the gate insulating film,

wherein the P-channel MOS transistor includes a p-type source region and a p-type drain region formed in the n-type shallow well region, a channel region formed between the p-type source region and the p-type drain region, a gate insulating film formed on the channel region, and a p-type gate electrode formed on the gate insulting film, and

wherein the n-type gate electrode is electrically connected to the p-type shallow well region, and the p-type gate electrode is electrically connected to the n-type shallow well region.

30. A semiconductor device according to claim 29, wherein the n-type deep well region is capable of functioning as an emitter or a collector of an npn type bipolar transistor;

the p-type shallow well region is capable of functioning as a base of the npn type bipolar transistor;

the n-type source region and the n-type drain region are capable of functioning as the collector or the emitter of the npn type bipolar transistor;

the p-type deep well region is capable of functioning as an emitter or a collector of a pnp type bipolar transistor;

the n-type shallow well region is capable of functioning as a base of the pnp bipolar transistor;

the p-type source region and the p-type drain region are capable of functioning as the collector or the emitter of the pnp bipolar transistor.

31. A semiconductor device according to claim 30, wherein the n-type gate electrode is electrically connected to the p-type shallow well region via source/drain regions of a first MOS transistor while the n-type drain region is electrically connected to a gate electrode of the first MOS transistor,

the p-type gate electrode is electrically connected to the n-type shallow well region via source/drain regions of a second MOS transistor while the p-type drain region is electrically connected to a gate electrode of the second MOS transistor, and

wherein the semiconductor device further comprises a p-type deeper well region which is deeper than the n-type deep well region, including the n-type deep well region, and an n-type deeper well region which is deeper than the p-type deep well region, including the p-type deep well region,

a potential of the n-type deep well region and a potential of the p-type deeper well region are set to be identical to each other, and a potential of the p-type deep well region and a potential of the n-type deeper well region are set to be identical to each other.

32. A semiconductor device according to claim 29, wherein adjacent n-type shallow well regions or adjacent p-type shallow well regions of adjacent elements are electrically separated from each other by a groove type element separation structure.

33. A semiconductor device according to claim 29, wherein the n-type shallow well region or the p-type shallow well region of the P-channel or N-channel MOS transistor which the p-type or n-type gate electrode is electrically connected to the n-type or p-type shallow well region is electrically separated from an n-type shallow well region or a p-type shallow well region of an adjacent MOS transistor which a p-type or n-type gate electrode is electrically connected to the n-type or p-type shallow well region by a groove type element separation structure and an impurity diffusion region which positions on a bottom of the groove type element separation structure and reaches the deep well region of an inverse conductivity type of the n-type or p-type shallow well region.

34. A semiconductor device according to claim 29, further comprising:

a second n-type well region surrounding the p-type deep well region, which is deeper than the p-type deep well region;

a second p-type well region surrounding the n-type deep well region, which is deeper than the n-type deep well region; and

a groove type element separation structure for separating the second n-type well region and the second p-type well region from each other.

35. A semiconductor device according to claim 29, wherein the p-type or n-type gate electrode includes a polycrystalline silicon film formed on the gate insulating film and a metal silicide film formed on the polycrystalline silicon film, and

wherein the metal silicide film is electrically connected to the n-type or p-type shallow well region via the contact region of the n-type or p-type shallow well region,

a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the n-type or p-type shallow well region is diffused at a higher concentration than that of a reminder of the n-type or p-type shallow well region, is formed in the contact region, and

an Ohmic contact is formed between the metal silicide film and the n-type or p-type shallow well region through the high concentration impurity diffusion region.

36. A semiconductor device according to claim 29, further comprising an interlayer insulating film and an upper wiring provided on the interlayer insulating film,

wherein a contact hole is formed in the interlayer insulating film, which penetrates through the p-type or n-type gate electrode and the gate insulating film so as to reach the contact region of the n-type or p-type shallow well region,

wherein a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the shallow well region is diffused at a higher concentration than that of a remainder of the shallow well region is formed in the contact region,

an Ohmic contact is formed between the upper wiring and the shallow well region through the high concentration impurity diffusion region on the bottom of the contact hole, and

wherein an Ohmic contact is formed between the gate electrode and the upper wiring on a side wall region of the contact hole.

37. A semiconductor device according to claim 29, wherein a difference of a potential formed between the n-type or p-type shallow well region and the source region and a difference of a potential formed between the n-type or p-type shallow well region and the drain region are set so as to be smaller than a built-in potential of a pn junction formed between source/drain regions and a shallow well region of a different conductivity type from the source/drain regions during operation.

38. A semiconductor device according to claim 29, wherein the gate electrode is electrically connected to the shallow well region via one of a second source region and a second drain region of a second MOS transistor, and a constant voltage is applied to a gate electrode of the second MOS transistor.

39. A semiconductor device according to claim 29, wherein the gate electrode is electrically connected to the shallow well region via one of a second source region and a second drain region of a second MOS transistor, and the drain region is connected to a second gate electrode of the second MOS transistor.

40. A semiconductor device according to claim 29, wherein a junction between at least bottoms of the p-type or n-type source/drain regions, and the n-type or p-type shallow well region, is doped with nitrogen ions or carbon ions.

41. A semiconductor device comprising a first block circuit or a second block circuit or both of the first and the second block circuits, wherein:

the first block circuit is positioned between a circuit block constituted by using the semiconductor device according to claim 29 and a power supply voltage source; and

the second block circuit is positioned between the circuit block and a ground voltage supply source,

wherein supply of a power supply voltage or supply of a ground voltage or both of the supply of the power supply voltage and the supply of the ground voltage are blocked when the circuit block is in a standby state.