Semiconductor P-I-N detector

• US 6,255,708 B1
• Filed: 10/10/1997
• Issued: 07/03/2001
• Est. Priority Date: 10/10/1997
• Status: Expired due to Term

• Current Assignee: Masimo Semiconductor Inc. (Masimo Corporation)
• Original Assignee: Methode Massachusettes, LLC
• Inventors: Sudharsanan, Rengarajan, Karam, Nasser H.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/949,015
• Time in Patent Office: 1,362 Days
• Field of Search: 257/441, 257/442, 257/458, 257/428, 250/370.13, 250/370.14, 250/370.09, 250/370.12
• US Class Current: 257/428
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/1828 the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
• CPC Class Codes: Y02E 10/543 Solar cells from Group II-VI materials

Abstract

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Claims

1. A multilayer semiconductor P-I-N device for detecting gamma rays, the device comprising:

an intrinsic wafer having a top surface and a bottom surface, the intrinsic wafer generating an electrical current as a function of impacting gamma rays,

a non-doped semiconductor boundary layer overlying the top surface of the intrinsic wafer,

a doped semiconductor layer overlying the non-doped semiconductor boundary layer, and

an oppositely doped semiconductor layer overlying the bottom surface of the intrinsic wafer,

wherein the non-doped semiconductor boundary layer positioned between the intrinsic wafer and the doped semiconductor layer reduces the diffusion of dopant into the intrinsic wafer, thereby reducing the leakage current through the P-I-N device.

2. A multilayer semiconductor P-I-N device according to claim 1, further including a second non-doped semiconductor boundary layer positioned between the intrinsic wafer and the oppositely doped semiconductor layer, such that leakage current through the P-I-N device is reduced.

3. A multilayer semiconductor P-I-N device according to claim 2, wherein:

the oppositely doped layer is formed of elements from groups II and VI of the periodic table and an N-type dopant, and

the second semiconductor boundary layer is formed of elements from groups II and VI of the periodic table.

4. A multilayer semiconductor P-I-N device according to claim 3, wherein:

the second semiconductor boundary layer is formed of cadmium sulfide, and

the oppositely doped layer is formed of cadmium sulfide doped with indium.

5. A multilayer semiconductor P-I-N device according to claim 1, wherein the semiconductor boundary layer has a thickness in the range of approximately 1.0 micrometers to approximately 2.0 micrometers.

6. A multilayer semiconductor P-I-N device according to claim 1, wherein:

the doped layer is formed of elements from groups II and VI of the periodic table and a P-type dopant, and

the semiconductor boundary layer is formed of elements from groups to and VI of the periodic table.

7. A multilayer semiconductor P-I-N device according to claim 6, wherein:

the semiconductor boundary layer is formed of zinc telluride, and

the doped layer is formed of zinc telluride doped with copper.

8. A multilayer semiconductor P-I-N device according to claim 1, wherein the doped semi conductor layer has a thickness in the range of approximately 0.25 micrometers to approximately 0.5 micrometers.

9. A multilayer semiconductor P-I-N device according to claim 1, wherein the intrinsic wafer includes materials selected from the group consisting of cadmium zinc telluride and cadmium telluride.

10. A multilayer semiconductor P-I-N device according to claim 8, wherein the intrinsic wafer includes cadmium zinc telluride crystals grown by High Pressure Bridgman techniques.

11. A multilayer semiconductor P-I-N device according to claim 1, wherein the intrinsic wafer has a thickness in the range of approximately 0.5 millimeters to approximately 10.0 millimeters.

12. A multilayer semiconductor P-I-N device according to claim 1, wherein the semiconductor boundary layer is formed of material deposited on the intrinsic wafer.

13. A multilayer semiconductor P-I-N device according to claim 12, wherein the oppositely doped semiconductor layer and the doped semiconductor layer are both formed of deposited material.

14. A multilayer semiconductor P-I-N device for detecting high energy rays, the device comprising:

an intrinsic wafer having a bottom surface and a top surface, the intrinsic wafer generating an electrical current as a function of impacting high energy rays,

a deposited non-doped semiconductor boundary layer overlying the top surface of the intrinsic wafer,

a doped semiconductor layer overlying the non-doped semiconductor boundary layer, and

an oppositely doped semiconductor layer deposited on and overlying the bottom surface of the intrinsic wafer,

wherein the non-doped semiconductor boundary layer positioned between the intrinsic wafer and the doped semiconductor layer reduces the diffusion of dopant into the intrinsic wafer, thereby reducing the leakage current through the P-I-N device.