Apparatus and method disabling and re-enabling access to IC test functions

• US 6,255,837 B1
• Filed: 05/09/2000
• Issued: 07/03/2001
• Est. Priority Date: 07/06/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kurth, Casey R., Mullarkey, Patrick J., Habersetzer, Daryl L., Graalum, Jason E.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US09/567,632
• Time in Patent Office: 420 Days
• Field of Search: 324/763, 324/765, 324/158.1, 365/201, 714/718, 714/724, 714/733, 714/734
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode

Abstract

A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the sane or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

Claims

1. A method for avoiding inadvertent entry into at least one test mode of a circuit, the method comprising:

providing a circuit having a first circuit in a disable state;

detecting at least a first signal at a signal level exceeding a threshold level greater than a specification rating signal level for the circuit;

detecting at least a second signal at a signal level exceeding the threshold level during detection of the at least a first signal; and

changing the first circuit from the disable state to an enable state in response to detecting the at least a first and at least a second signals.

2. The method of claim 1, further comprising maintaining the first circuit in the enable state after changing the first circuit to the enable state, regardless of whether the at least a first and at least a second signals are subsequently detected.

3. The method of claim 2, wherein the method comprises avoiding inadvertent entry into at least one test mode of an integrated circuit.

4. The method of claim 1, wherein changing the first circuit from the disable state to the enable state in response to detecting the first and second signals comprises:

producing a test-key enable signal at a second circuit in response to detecting the at least a first and at least a second signals;

detecting the test-key enable signal at the first circuit; and

changing the first circuit from the disable state to the enable state in response to detecting the test-key enable signal.