Integrated circuit having dynamic logic with reduced standby leakage current

• US 6,255,853 B1
• Filed: 09/29/1998
• Issued: 07/03/2001
• Est. Priority Date: 09/29/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/162,865
• Time in Patent Office: 1,008 Days
• Field of Search: 326/98, 326/95, 326/93, 326/96, 326/97, 326/83, 326/119, 326/121, 326/112
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

An integrated circuit (10) is disclosed that has a dynamic logic stage (12) with reduced standby leakage current. The integrated circuit (10) includes a logic gate (20) coupled to a dynamic node (NODE 1) of the dynamic logic stage (12). The logic gate (20) has a first voltage supply terminal and a second voltage supply terminal. The logic gate (20) consumes standby leakage current when the dynamic logic stage (12) is not in an evaluation phase or when the clock is idle. A transistor (30) has a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal. The drain of the transistor (30) provides an intermediate node (NODE 4) for supplying voltage to the logic gate (20). The transistor (30) is operable to be turned off by the control signal when the dynamic logic stage (12) is not in an evaluation phase or the dynamic logic section is in standby such that the transistor (30) reduces the standby leakage current of the logic gate (20). In addition, a sub-circuit, such as transistor (34), can be used to limit the voltage difference between the first voltage supply and a voltage level of the intermediate node (NODE 4).

Claims

1. An integrated dynamic logic circuit, comprising:

a logic gate having a high voltage end and a relatively low voltage end;

a dynamic node coupled to said high voltage end of said logic gate;

a first relatively high voltage supply terminal coupled to said high voltage end of said logic gate and said dynamic node and a second relatively low voltage supply terminal coupled to said low voltage end of said logic gate;

a first semiconductor device having a current path and a control electrode, one end of said current path connected to said first relatively high voltage supply terminal and the other end of said current path connected to said dynamic node;

relatively low threshold voltage circuitry coupled to said node having a relatively low threshold voltage and normally consuming standby leakage current; and

a second relatively high threshold voltage semiconductor device having a current path coupled between said first relatively high voltage supply and said relatively low threshold voltage circuitry and having a control electrode, said second semiconductor device being turned off when said first semiconductor device is turned on and vice versa to reduce the standby leakage current of the logic gate.

2. The integrated circuit of claim 1, wherein:

said logic gate is in an evaluation phase when said first semiconductor device is non-conducting and said second semiconductor device is conducting;

the logic gate consuming standby leakage current when the dynamic logic gate is not in an evaluation phase.

4. The integrated circuit of claim 1, wherein the first semiconductor device is a P-channel transistor.

5. The integrated circuit of claim 1, wherein the relatively low threshold voltage circuitry is an inverter.

6. The integrated circuit of claim 5, wherein the inverter comprises:

a P-channel transistor having a source connected to the high voltage terminal of the inverter, a gate connected to the dynamic node, and a drain; and

an N-channel transistor having a drain connected to the drain of the P-channel transistor, a gate connected to the dynamic node, and a source connected to the low voltage terminal of the inverter.

3. An integrated circuit having a dynamic logic stage, comprising

a logic gate coupled to a dynamic node of the dynamic logic stage, the logic gate having a first voltage supply terminal and a second voltage supply terminal;

and

a transistor having a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal, such that the drain of the transistor provides an intermediate node for supplying voltage to the logic gate;

the logic gate consuming standby leakage current; and

the transistor turned off by the control signal, such that the transistor reduces the standby leakage current of the logic gate;

the logic gate consuming standby leakage current when the dynamic logic stage is not in an evaluation phase; and

the transistor being turned off by the control signal when the dynamic logic stage is not in the evaluation phase;

wherein the logic gate consumes standby leakage current when the dynamic logic stage is in standby; and

the transistor is turned off by the control signal when the dynamic logic stage is in standby.

7. An integrated circuit having a dynamic logic stage, comprising:

a logic gate coupled to a dynamic node of the dynamic logic stage, the logic gate having a first voltage supply terminal and a second voltage supply terminal; and

a transistor having a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal, such that the drain of the transistor provides an intermediate node for supplying voltage to the logic gate;

the logic gate consuming standby leakage current; and

the transistor turned off by the control signal, such that the transistor reduces the standby leakage current of the logic gate;

wherein the control signal is substantially an inverse of a clock signal for the dynamic logic stage.

8. An integrated circuit having a dynamic logic stage, comprising:

a logic gate coupled to a dynamic node of the dynamic logic stage, the logic gate having a first voltage supply terminal and a second voltage supply terminal; and

a transistor having a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal, such that the drain of the transistor provides an intermediate node for supplying voltage to the logic gate;

the logic gate consuming standby leakage current; and

the transistor turned off by the control signal, such that the transistor reduces the standby leakage current of the logic gate;

wherein the control signal is a standby signal for the dynamic logic stage.

9. An integrated circuit having a dynamic logic stage, comprising:

a logic gate coupled to a dynamic node of the dynamic logic stage, the logic gate having a first voltage supply terminal and a second voltage supply terminal; and

a transistor having a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal, such that the drain of the transistor provides an intermediate node for supplying voltage to the logic gate;

the logic gate consuming standby leakage current; and

the transistor turned off by the control signal, such that the transistor reduces the standby leakage current of the logic gate;

wherein the control signal is a sleep signal for the dynamic logic stage.

10. An integrated circuit having a dynamic logic stage, comprising:

a logic gate coupled to a dynamic node of the dynamic logic stage, the logic gate having a first voltage supply terminal and a second voltage supply terminal; and

a transistor having a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal. such that the drain of the transistor provides an intermediate node for supplying voltage to the logic gate;

the logic gate consuming standby leakage current; and

the transistor turned off by the control signal, such that the transistor reduces the standby leakage current of the logic gate;

further comprising a second logic gate coupled to a dynamic node of the dynamic logic stage, the second logic gate having a first voltage supply terminal and a second voltage supply terminal, and the first voltage supply terminal of the second logic gate connected to the intermediate node, such that the transistor also reduces the standby leakage current of the second logic gate.

11. An integrated circuit, comprising:

a dynamic logic stage, an intermediate node, a source of clock signals for said dynamic logic stage and a source of control signals;

a first transistor for enabling said dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage and intermediate node, a source connected to a first voltage supply and a gate connected to the source of clock signals for the dynamic logic stage; and

a second relatively high transition voltage transistor having a source connected to said first voltage supply, a drain connected through a relatively low transition voltage circuit to said intermediate node, and a gate connected to said source of control signals, said intermediate node providing said first voltage supply for the dynamic logic stage when said first transistor is on or in the non-evaluation phase and said second transistor is off or in the non-evaluation phase;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase; and

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase to reduce the standby leakage current of the dynamic logic stage.

12. The integrated circuit of claim 11, further comprising a sub-circuit connected between the intermediate node and the first voltage supply, the sub-circuit limiting a voltage difference between the first voltage supply and the intermediate node to a predetermined amount.

13. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase, such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

a third transistor having a source connected to the intermediate node, a drain connected to the first voltage supply and a gate connected to the first voltage supply;

the third transistor operating to limit the voltage difference between the first voltage supply and the intermediate node.

16. The integrated circuit of claim 13, wherein the third transistor is a P-channel transistor.

14. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase, such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

wherein the first voltage supply is a low voltage supply.

15. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase, such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

wherein the first transistor and the second transistor are N-channel transistors.

17. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase, such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

wherein the control signal is substantially an inverse of a standby signal for the dynamic logic stage.

18. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase, such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

wherein the control signal is substantially an inverse of a sleep signal for the dynamic logic stage.

19. An integrated circuit having a dynamic logic stage, comprising:

a first transistor used to enable a dynamic logic stage, the first transistor having a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage; and

a second transistor having a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal, such that the intermediate node provides a first voltage supply for the dynamic logic stage;

the dynamic logic stage consuming standby leakage current when the dynamic logic stage is not in an evaluation phase;

the second transistor being turned off by the control signal when the dynamic logic stage is not in an evaluation phase such that the second transistor reduces the standby leakage current of the dynamic logic stage; and

further comprising a third transistor used to enable a second dynamic logic stage, the third transistor having a drain connected to the second dynamic logic stage, a source connected to the intermediate node and a gate connected to the clock signal, such that the second transistor also reduces the standby leakage current of the second dynamic logic stage.

20. An integrated circuit having a dynamic logic stage, comprising:

a first voltage supply;

a clocked relatively high threshold voltage transistor forming part of the dynamic logic stage, the clocked transistor having a source, a drain and a clocked gate; and

a second relatively low threshold voltage transistor having a source connected to said first voltage supply, a drain connected to the source of the clocked transistor, and a gate connected to a control signal, the drain of the second transistor providing an intermediate node for supplying voltage to the clocked transistor;

the clocked transistor consuming standby leakage current; and

the second transistor turned off by the control signal, such that the second transistor reduces the standby leakage current of the logic gate.

21. An integrated circuit having a dynamic logic stage, comprising:

a clocked transistor forming part of the dynamic logic stage, the clocked transistor having a source and a drain; and

a second transistor having a source connected to a first voltage supply, a drain connected to the source of the clocked transistor, and a gate connected to a control signal, such that the drain of the second transistor provides an intermediate node for supplying voltage to the clocked transistor;

the clocked transistor consuming standby leakage current; and

the second transistor turned off by the control signal, such that the second transistor reduces the standby leakage current of the logic gate;

the clocked transistor consumes standby leakage current when the dynamic logic stage is not in an evaluation phase; and

the second transistor is turned off by the control signal when the dynamic logic stage is not in the evaluation phase.

22. An integrated circuit having a dynamic logic stage, comprising:

a clocked transistor forming part of the dynamic logic stage, the clocked transistor having a source and a drain; and

a second transistor having a source connected to a first voltage supply, a drain connected to the source of the clocked transistor, and a gate connected to a control signal, such that the drain of the second transistor provides an intermediate node for supplying voltage to the clocked transistor;

the clocked transistor consuming standby leakage current; and

the second transistor turned off by the control signal, such that the second transistor reduces the standby leakage current of the logic gate;

the clocked transistor consumes standby leakage current when the dynamic logic stage is in standby; and

the second transistor is turned off by the control signal when the dynamic logic stage is in standby.

23. A method for reducing standby leakage current through a logic gate connected to a dynamic logic stage, comprising:

connecting a relatively high threshold voltage leakage current reducing transistor to a first voltage supply, the leakage current reducing transistor providing a controllable current path between the high voltage supply and an intermediate node;

connecting a first voltage terminal of a relatively low threshold voltage logic gate to the intermediate node, the logic gate consuming standby leakage current; and

turning off the current path of the leakage current reducing transistor, such that the leakage current reducing transistor reduces the standby leakage current of the logic gate.

24. The method of claim 23, wherein:

the logic gate consumes standby leakage current when the dynamic logic stage is not in an evaluation phase; and

the current path of the leakage current reducing transistor is turned off when the dynamic logic stage is not in an evaluation phase.

25. A method for reducing standby leakage current through a logic gate connected to a dynamic logic stage, comprising:

connecting a leakage current reducing transistor to a first voltage supply, the leakage current reducing transistor providing a controllable current path between the high voltage supply and an intermediate node;

connecting a first voltage terminal of a logic gate to the intermediate node, the logic gate consuming stand by leakage current; and

turning off the current path of the leakage current reducing transistor, such that the leakage current reducing transistor reduces the standby leakage current of the logic gate;

the logic gate consuming standby leakage current when the dynamic logic stage is in standby; and

the current path of the leakage current reducing transistor being turned off when the dynamic logic stage is in standby.

26. A method for reducing standby leakage current through a logic gate connected to a dynamic logic stage, comprising:

connecting a leakage current reducing transistor to a first voltage supply, the leakage current reducing transistor providing a controllable current path between the high voltage supply and an intermediate node;

connecting a first voltage terminal of a logic gate to the intermediate node, the logic gate consuming stand by leakage current; and

turning off the current path of the leakage current reducing transistor, such that the leakage current reducing transistor reduces the standby leakage current of the logic gate;

further comprising limiting a voltage difference between the first voltage supply and the intermediate node.

27. The method of claim 26, wherein limiting is accomplished by connecting a keeper transistor between the first voltage supply and the intermediate node, such that the keeper transistor operates to limit the voltage difference between the first voltage supply and the intermediate node.

28. An integrated circuit which comprises:

a voltage source having a relatively high voltage terminal and a relatively low voltage terminal;

a logic circuit coupled across said voltage source including a logic gate and a pair of clock operated switches, one of said pair of switches at opposite ends of said logic gate, said logic gate connected in series with said pair of switches and having a dynamic node at the junction of said logic circuit and one of said clock operated switches at the high voltage end of said logic gate;

a relatively high threshold voltage switch coupled at one end thereof to said relatively high voltage terminal;

circuitry under control of said node having a relatively low threshold voltage coupled at one end thereof to the other end of said relatively high threshold voltage switch and at the other end thereof to said relatively low voltage terminal.

29. The circuit of claim 28 wherein said circuitry is an inverter.

30. The circuit of claim 28 wherein said pair of switches are alternately conducting or non-conducting.

31. The circuit of claim 29 wherein said pair of switches are concurrently conducting or non-conducting.

32. The circuit of claim 31 wherein said relatively high threshold voltage switch is conducting when the one of said pair of switches that is at the high voltage end is non-conducting.