Track-and-hold circuit

• US 6,255,865 B1
• Filed: 11/03/1999
• Issued: 07/03/2001
• Est. Priority Date: 11/03/1999
• Status: Expired due to Fees

• Current Assignee: Innurvation IP LLC
• Original Assignee: Nanopower Technologies, Inc.
• Inventors: Opris, Ion E.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/433,838
• Time in Patent Office: 608 Days
• Field of Search: 327/91, 327/93, 327/94, 327/95, 327/96, 327/97, 327/72
• US Class Current: 327/94
• CPC Class Codes: A63F 3/081 electric
• CPC Class Codes: G06Q 20/04 Payment circuits
• CPC Class Codes: G07F 17/3244 Payment aspects of a gaming system, e.g. payment schemes, setting payout ratio, bonus or consolation prizes
• CPC Class Codes: G07F 17/3248 involving non-monetary media of fixed value, e.g. casino chips of fixed value
• CPC Class Codes: G07F 17/3262 Player actions which determine the course of the game, e.g. selecting a prize to be won, outcome to be achieved, game to be played
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A method and apparatus for an improved track-and-hold circuit is disclosed. By utilizing an amplifier connected to the input signal in combination with, in essence, a replica of the track-and-hold sampling transistor, a track-and-hold technique that reduces distortion and nonlinearities in the sampling process is achieved.

Claims

1. A method of controlling a sampling device in a track-and-hold circuit, the method comprising:

receiving an input signal; and

using the input signal to control an impedance of the sampling device including;

amplifying the received input signal.

2. The method, according to claim 1, wherein said receiving an input signal comprises receiving an input signal to be sampled.

3. The method, according to claim 2, wherein said using the input signal to control an impedance of the sampling device further includes using the amplified input signal to control the impedance of the sampling device, such that the sampling device has a substantially constant impedance over a specified range of amplitudes of the input signal.

4. A method of controlling a sampling device in a track-and-hold circuit, the method comprising:

receiving an input signal; and

using the input signal to control an impedance of the sampling device including;

amplifying the received input signal;

applying a proportion of the amplified received input signal to the sampling device;

measuring the voltage on the sampling device;

measuring the voltage of the received input signal;

calculating a difference between the voltage on the sampling device and the voltage of the received input signal;

comparing the difference with a predetermined desired constant; and

adjusting the proportion of the amplified received input signal to the sampling device to minimize the difference.

5. A method of controlling a sampling device in a track-and-hold circuit, comprising:

receiving an input signal to be sampled by the sampling device, wherein the input signal has an amplitude having a usable range;

amplifying the input signal; and

using the amplified input signal to control the sampling device, such that the sampling device has a substantially constant impedance over the usable range of the input signal amplitude.

6. A method of controlling a sampling device in a track-and-hold circuit, comprising:

determining the voltage of an input signal;

amplifying the input signal; and

maintaining a substantially fixed voltage between the input signal and the sampling device.

7. A method for obtaining an input signal sample, comprising:

coupling an input signal to a sampling device, the sampling device having characteristics;

coupling the input signal to a control device input wherein the control device comprises an amplifier; and

using the control device output to affect the sampling device such that the characteristics of the sampling device are substantially constant over a usable range of the input signal.

8. A method according to claim 7, wherein the sampling device is a transistor.

9. A method according to claim 8, wherein the transistor is a metal-oxide-semiconductor transistor (MOS).

10. A method according to claim 7, wherein the amplifier in the control device includes a buffer amplifier coupled to a like sampling device.

11. A method according to claim 10, wherein the like sampling device is a transistor.

12. A method according to claim 11, wherein the transistor is a metal-oxide-semiconductor transistor (MOS).

13. A track-and-hold circuit comprising:

a first transistor, the first transistor having a control terminal, an input terminal, and an output terminal, wherein the input terminal is coupled to receive an input signal;

a sampling capacitor, the output terminal of first transistor coupled to the sampling capacitor;

an amplifier, the amplifier having an input and an output, the input signal coupled to the input of the amplifier; and

a second transistor, the second transistor having a control terminal, an input terminal, and an output terminal, the output of the amplifier coupled to the input terminal of the second transistor, the control terminal of the second transistor coupled to the output of the second transistor and the control terminal of the first transistor.

14. The circuit in claim 13, wherein the first and second transistor are metal-oxide-semiconductor (MOS) transistors.

15. The circuit in claim 13, wherein the amplifier has a gain of substantially unity.

16. The circuit in claim 13, wherein the first and second transistor are substantially similar.

17. An analog-to-digital conversion system comprising:

an analog signal input source;

timing control circuitry for controlling the analog signal input source to digital conversion process; and

a track-and-hold input section, coupled to the analog signal input source, and having;

a first transistor, the first transistor having a control terminal, an input terminal, and an output terminal, an input signal coupled to the input terminal of the first transistor;

a sampling capacitor, the output terminal of the first transistor coupled to the sampling capacitor;

an amplifier, the amplifier having an input and an output, the input signal coupled to the input of the amplifier;

a second transistor, the second transistor having a control terminal, an input terminal, and an output terminal, the output of the amplifier coupled to the input terminal of the second transistor; and

the control terminal of the second transistor coupled to the output of the second transistor and the control terminal of the first transistor.

18. The analog-to-digital conversion system as recited in claim 17, further comprising:

an Integrated Circuit (IC) chip wherein, the first and second transistor are on the IC chip.

19. A track-and-hold circuit comprising:

means for receiving an input signal to be sampled by a sampling device, wherein the input signal has an amplitude having a usable range;

means for amplifying the input signal; and

means for providing the amplified input signal to the sampling device so as to maintain a substantially constant impedance of the sampling device.

20. A track-and-hold circuit comprising:

a sampling device, the sampling device having an input, an output, and a control terminal;

an amplifier having an input and an output;

a sample storage device having an input; and

wherein an input signal is coupled to the input of the sampling device and the input of the amplifier, and the output of the amplifier is coupled to the control terminal of the sampling device, and the output of the sampling device is coupled to the input of the sample storage device.

21. A track-and-hold circuit comprising:

a sampling transistor, coupled to receive an input signal; and

a second transistor substantially the same as the sampling transistor, coupled to the input signal through an amplifier and biasing the sampling transistor.

22. A track-and-hold method, the method comprising:

receiving an input signal to be sampled with a sampling device having characteristics;

receiving the input signal at a sampling device driver;

amplifying the input signal;

controlling the sampling device characteristics with the sampling device driver such that the sampled input signal has substantially lowered nonlinearities; and

storing the sampled input signal.