Circuit and method for high speed bit stream capture using a digital delay line

• US 6,255,969 B1
• Filed: 12/18/1997
• Issued: 07/03/2001
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Crayford, Ian
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/992,949
• Time in Patent Office: 1,293 Days
• Field of Search: 341/100, 341/101, 341/143, 375/130, 375/138, 375/373, 377/20, 326/50, 326/62
• US Class Current: 341/100
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 2005/00084 by trimming or adjusting the delay
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A digital delay line, comprising adjustable digital delay elements, receives and buffers an incoming bit stream by repeatedly delaying bits of the bit stream for a specific period of time. The outputs of selected adjustable digital delay elements are tapped for inspecting in parallel a specific pattern of bits of the bit stream. A programmable counter counts bit periods and generates a latch control signal to latch those specific bits at any offset within the bit stream before the entirety of the bit stream is received.

Claims

1. A high-speed bit stream capture circuit, comprising:

a transmission interface unit for receiving an incoming bit stream and producing therefrom a high-speed bit stream;

a digital delay line coupled to said transmission interface unit, including a plurality of digital delay elements coupled in series and a plurality of taps, each tap coupled to the output of a distinct digital delay element of said plurality of digital delay elements, for receiving and delaying the high-speed bit stream;

a latch having a plurality of latch inputs, each latch input being coupled to a respective tap of said plurality of taps, and a latch control input for receiving a latch control signal for latching and outputting through a plurality of latch outputs parallel data at said plurality of latch inputs; and

a counter for counting to a prescribed number of bit stream periods from the start of said bit stream and, when said prescribed number of bit stream periods is counted, generating said latch control signal.

2. The high-speed bit capture circuit of claim 1, wherein:

said digital delay line further includes a calibration input for receiving a calibration signal; and

each of said plurality of digital delay elements comprises a calibration input for receiving said calibration signal and in response adjusts the delay period thereof.

3. The high-speed bit stream capture circuit of claim 2, wherein each digital delay element comprises:

a first adjustable inverter, having a first calibration input for receiving said calibration signal; and

a second adjustable inverter, having a second calibration input for receiving said calibration signal, coupled in series to said first switchable inverter.

4. The high-speed bit stream capture circuit of claim 1, wherein the delay period of each of said plurality of digital delay elements is the same.

5. The high-speed bit stream capture circuit of claim 1, wherein the delay period of each of said plurality of digital delay elements is at least 140 ps.

6. The high-speed bit capture circuit of claim 1, wherein each of said plurality latch inputs is coupled to a respective tap of said plurality of taps.

7. The high-speed bit capture circuit of claim 1, wherein said counter is configured for modifying said prescribed number according to a signal indicative of a new prescribed number of bit stream periods.

8. The high-speed bit capture circuit of claim 1, wherein the prescribed number is less than the total number of bit stream periods in said bit stream.

9. The high-speed bit capture circuit of claim 1, wherein said transmission interface unit includes a buffer for receiving a single ended bit stream and producing therefrom said high-speed bit stream applied to said digital delay line.

10. The high-speed bit capture circuit of claim 9, wherein said transmission interface unit includes a level shifter for shifting the voltage level of said single ended bit stream.

11. The high-speed bit capture circuit of claim 1, wherein said transmission interface unit includes a comparator for comparing a differentially encoded bit stream and producing therefrom said high-speed bit stream applied to said digital delay line.

12. A method of capturing bits from a high-speed bit stream, comprising the steps of:

receiving the high-speed bit stream;

repeatedly delaying by a delay period a plurality of bits from said high-speed bit stream;

tapping said plurality of bits in parallel to produce parallel data;

counting bit stream periods of said high-speed bit stream; and

latching said parallel data when a prescribed number of bit stream periods is counted.

13. The method of claim 12, further comprising the step of calibrating said delay period to be the same as said bit stream period.

14. The method of claim 12, further comprising the step of changing said prescribed number.

15. The method of claim 12, wherein said parallel data is latched before the entire said bit stream is delayed.

16. The method of claim 12, further comprising the step of level shifting said high-speed bit stream before said repeatedly delaying said high-speed bit stream.

17. The method of claim 12, further comprising the step of comparing differentially encoded voltages of said high-speed bit stream to produce a single ended bit stream.

18. The method of claim 12, wherein the step of repeated delaying includes the steps of applying the high-speed bit stream to a digital delay line.