Configurable data converter
First Claim
1. An embedded digital system, comprising:
- a data converter; and
a converter configuration register adapted to changeably define a conversion mode of said data converter on a bitwise basis with respect to a data frame.
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Accused Products
Abstract
A/D converter or as a D/A converter forms a data converter embedded in a digital circuit for reconfigurable use. Conversion parameters of the data converter are controlled on a bitwise basis from a bitwise converter configuration register. For instance, output locations (i.e., time slots) of the data converter are determined by a bitwise converter configuration register, as is the selection of a D/A conversion mode or A/D conversion mode of the data converter for that particular output location, and/or the output sample length are controlled by appropriate signals from the bitwise converter configuration register. The bitwise converter configuration register also preferably configures the input source to the data converter and/or to an interface, e.g., to a parallel-to-serial, serial-to-serial, or parallel-to-parallel interface device, on a bitwise basis, to provide flexibility both in the source of the channels as well as the output location of particular channels in the data frame.
15 Citations
24 Claims
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1. An embedded digital system, comprising:
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a data converter; and
a converter configuration register adapted to changeably define a conversion mode of said data converter on a bitwise basis with respect to a data frame. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
said data converter includes a first mode operating as a digital-to-analog converter and a second mode operating as an analog-to-digital converter.
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3. The embedded digital system according to claim 2, wherein:
said data converter functions as a successive approximation converter when operating in said analog-to-digital mode.
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4. The embedded digital system according to claim 1, wherein:
said converter configuration register selectably configures said data converter as one of a digital-to-analog converter and an analog-to-digital converter.
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5. The embedded digital system according to claim 1, wherein:
said converter configuration register selectably directs an input to said data converter on a bitwise basis.
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6. The embedded digital system according to claim 1, wherein:
said converter configuration register selectably defines a sample length of an output from said data converter for a respective portion of said data frame.
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7. The embedded digital system according to claim 6, wherein:
said sample length is at least 13 bits.
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8. The embedded digital system according to claim 7, wherein:
said portion of said data frame is at least 16 clock cycles in length.
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9. A method of selectably configuring a serial data frame including a plurality of conversion data, comprising:
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setting a conversion mode of a data converter for a particular one of a plurality of conversions performed by said data converter; and
defining a location for an output of said particular conversion in said serial data frame. - View Dependent Claims (10, 11, 12)
changeably setting a sample size of each sample output from said data converter.
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11. The method of selectably configuring a serial data frame including a plurality of conversion data according to claim 10, wherein:
said sample size is at least 13 bits.
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12. The method of selectably configuring a serial data frame including a plurality of conversion data according to claim 9, wherein:
said conversion mode of said particular conversion is set to one of a digital-to-analog conversion mode and an analog-to-digital conversion mode.
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13. Apparatus for selectably configuring a serial data frame including a plurality of conversion data, comprising:
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means for setting a conversion mode of a data converter for a particular one of a plurality of conversions performed by said data converter; and
means for defining a location for an output of said particular conversion in said serial data frame. - View Dependent Claims (14, 15, 16, 19)
means for changeably setting a sample size of each sample output from said data converter.
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15. The apparatus for selectably configuring a serial data frame including a plurality of conversion data according to claim 14, wherein:
said sample size is at least 13 bits.
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16. The apparatus for selectably configuring a serial data frame including a plurality of conversion data according to claim 13, wherein:
said conversion mode of said particular conversion is adapted to be set to one of a digital-to-analog conversion mode and an analog-to-digital conversion mode.
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19. The method of configuring an embedded digital system according to claim 16, wherein:
said step of converting data functions as a successive approximation converter when operating in said analog-to-digital mode.
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17. A method of configuring an embedded digital system, comprising:
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converting data; and
configuring a converter register to changeably define a conversion mode of said converted data on a bitwise basis with respect to a data frame containing said data. - View Dependent Claims (18, 20, 21, 22, 23, 24)
said step of converting data includes a first mode operating as a digital-to-analog converter and a second mode operating as an analog-to-digital converter.
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20. The method of configuring an embedded digital system according to claim 17, wherein:
said step of configuring a converter register selectably configures said converted data as one of a digital-to-analog converter and an analog-to-digital converter.
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21. The method of configuring an embedded digital system according to claim 17, wherein:
said step of configuring a converter register selectably directs an input to said data converter on a bitwise basis.
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22. The method of configuring an embedded digital system according to claim 17, wherein:
said step of configuring a converter register selectably defines a sample length of an output from said data converter for a respective portion of said data frame.
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23. The method of configuring an embedded digital system according to claim 22, wherein:
said sample length is at least 13 bits.
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24. The method of configuring an embedded digital system according to claim 23, wherein:
said portion of said data frame is at least 16 clock cycles in length.
Specification