Construction and application for non-volatile reprogrammable switches
First Claim
1. A non-volatile, reprogrammable switch, comprising:
- a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a capacitor formed in a subsequent layer above the first MOSFET and separated from the MOSFET by an insulator layer; and
a vertical electrical via coupling a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET; and
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET.
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Abstract
The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions.
The present invention includes applications such as a very size efficient address decode tree, data routing device, or other applications such as used in DRAM redundancy schemes. Methods for forming and using the present invention are also included. The need for intervening sense amps normally required to read the status of a non-volatile memory cell (e.g. an EEPROM cell) and communicate this to additional logic that would then in turn control the status of one or more switches is eliminated. Thus, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.
45 Citations
57 Claims
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1. A non-volatile, reprogrammable switch, comprising:
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a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a capacitor formed in a subsequent layer above the first MOSFET and separated from the MOSFET by an insulator layer; and
a vertical electrical via coupling a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET; and
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A non-volatile, reprogrammable switch, comprising:
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a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and
an electrical contact coupling a bottom plate of the stacked capacitor through the insulator layer to a gate of first MOSFET; and
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A non-volatile, reprogrammable switch, comprising:
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a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a stacked capacitor formed in a subsequent layer above the first MOSFET and separated from the MOSFET by an insulator layer; and
a vertical electrical via coupling a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET;
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET; and
a third MOSFET formed in the semiconductor substrate, wherein the gate of the first and second MOSFET also serves as a gate of the third MOSFET. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A data decoding device, comprising:
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a number of non-volatile, reprogrammable switches, wherein each non-volatile, reprogrammable switch includes;
a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a capacitor formed in a subsequent layer above the first MOSFET and separated from the MOSFET by an insulator layer; and
a vertical electrical via coupling a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET; and
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET;
a number of programming control lines coupled to the non-volatile memory cells in the number of non-volatile, reprogrammable switches;
a number of input bit lines coupled to an input node for the second MOSFET in the number of non-volatile, reprogrammable switches; and
a number of output bit lines coupled to an output node for the second MOSFET in the number of non-volatile, reprogrammable switches. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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31. A data routing device, comprising:
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a number of non-volatile, reprogrammable switches, wherein each non-volatile, reprogrammable switch includes;
a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a capacitor; and
a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of first MOSFET;
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET; and
a third MOSFET formed in the semiconductor substrate, wherein the gate of the first and second MOSFET also serves as a gate of the third MOSFET;
a number of programming control lines coupled to the non-volatile memory cells in the number of non-volatile, reprogrammable switches;
a number of input bit lines coupled to an input node for the second MOSFET and to an input node for the third MOSFET in the number of non-volatile, reprogrammable switches; and
a number of output bit lines coupled to an output node for the second MOSFET and to an output node for the third MOSFET in the number of non-volatile, reprogrammable switches. - View Dependent Claims (32, 33, 34, 35, 36, 37)
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38. An electronic system, comprising:
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a processor;
a dynamic random access memory (DRAM) chip; and
a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes an array of non-volatile, reprogrammable switches, wherein each non-volatile, reprogrammable switch includes;
a non-volatile memory cell, wherein the non-volatile memory cell includes;
a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;
a stacked capacitor; and
a vertical electrical via coupling a bottom plate of the stacked capacitor through an insulator layer to a gate of first MOSFET; and
a second MOSFET formed in the semiconductor substrate, wherein the gate of the first MOSFET also serves as a gate of the second MOSFET. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A method for operating a non-volatile, reprogrammable switch, comprising:
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controlling a charge on a gate of a first metal oxide semiconductor field effect transistor (MOSFET), wherein controlling the charge on the gate of the first MOSFET includes controlling a charge on a bottom plate of a stacked capacitor, wherein the bottom plate of the stacked capacitor is coupled to the gate of the first MOSFET through an insulator layer, and wherein the gate of the first MOSFET is shared as a gate for a second MOSFET; and
applying a first signal to a first diffused region for the second MOSFET; and
outputting a second signal from a second diffused region for the second MOSFET to another circuit component on an integrated circuit. - View Dependent Claims (49, 50)
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51. A method for operating a switching element, comprising:
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sharing a gate between a first, a second, and a third MOSFET;
placing a charge on the gate, wherein placing a charge on the gate includes applying a control voltage to a top plate of a stacked capacitor located above the first MOSFET, wherein a bottom plate of the stacked capacitor is coupled by a vertical electrical via through an insulator to the gate; and
reading a current conducted through the second MOSFET. - View Dependent Claims (52, 53, 54)
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55. A method for operating a switching element, comprising:
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sharing a gate between a non-volatile memory cell and a first, and a second, MOSFET, wherein the gate is a floating gate for the non-volatile memory cell;
programming the non-volatile memory cell in either a first or a second programmed state; and
reading a current conducted through the first MOSFET. - View Dependent Claims (56, 57)
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Specification