Apparatus and method for programming voltage protection in a non-volatile memory system

• US 6,256,229 B1
• Filed: 03/01/2000
• Issued: 07/03/2001
• Est. Priority Date: 01/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): Zarabian, A.
• Application Number:
  US09/516,532
• Time in Patent Office: 489 Days
• Field of Search: 365/189.18, 365/226, 365/228, 365/189.07
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A memory system includes a memory cell array, a controller, a programming voltage node for receiving a programming voltage, and a voltage detection circuit including a voltage divider circuit switchable between first and second states. In the first state, the divider circuit produces first, second and third intermediate voltages at first, second and third nodes when the programming voltage is at first, second, and third levels. In the second state, the divider circuit produces the first, second and third intermediate voltages at the first, second and third nodes when the programming voltage is at fourth, fifth and sixth levels. The first voltage level is greater than the fourth level. The detection circuit also includes control circuitry to enable the controller to initiate a program operation when the programming voltage exceeds the first level and to terminate an initiated program operation when that voltage drops below the fourth level.

Claims

1. A memory system comprising:

an array of memory cells;

a memory controller which controls memory programming operations of the memory system;

a programming voltage node configured to receive a first programming voltage;

a voltage detection circuit, operably coupled to the programming voltage node and the memory controller, said voltage detection circuit comprising a voltage divider circuit switchable between a first state and a second state, with the voltage divider circuit being configured to produce, when in the first state, a first intermediate voltage at a first node when the first programming voltage is at a first level, a second intermediate voltage at a second node when the first programming voltage is at a second level and a third intermediate voltage at a third node when the first programming voltage is at a third level and with the voltage divider circuit being configured to produce, when in the second state, the first intermediate voltage at the first node when the first programming voltage is at a fourth level, the second intermediate voltage at the second node when the first programming voltage is at a fifth level, and the third intermediate voltage at the third node when the first programming voltage is at a sixth level, with the first voltage level being greater than the fourth voltage level; and

said voltage detection circuit further comprising control circuitry, operably coupled to the first node of the voltage divider circuit, said control circuitry being configured to enable the memory controller to initiate a memory program operation when the first programming voltage exceeds the first level and to cause the memory controller to terminate an initiated program operation when the first programming voltage drops below the fourth level.

2. The memory system of claim 1 wherein the voltage divider circuit is further configured to produce, when in the second state, the second intermediate voltage at the second node when the first programming voltage is at the fifth level and the third intermediate voltage at the third node when the first programming voltage is at the sixth level, with the third voltage level being greater than the sixth voltage level, with said control circuitry being operably coupled to the third node and configured to enable the memory controller to initiate a memory program operation when the first programming voltage exceeds the third voltage level and to cause the memory controller to terminate an initiated memory programming operation when the first programming voltage drops below the sixth voltage level.

3. The memory system of claim 1 wherein the control circuitry comprises a first comparator circuit having a first input coupled to the first node, a second comparator circuit having a first input coupled to the second node and a third comparator circuit having a first input coupled to the third node.

4. The memory system of claim 3 wherein the control circuitry further comprises combinational logic circuitry operably coupled to outputs of the first, second and third comparator circuits, with said combinational logic circuitry configured to enable the memory controller to initiate and terminate the memory programming operations.

5. The memory system of claim 4 wherein the voltage divider circuit consumes more electrical power in the first state than in the second state.

6. The memory system of claim 5 wherein the voltage divider circuit consumes an order of magnitude more electrical power in the first state than in the second state.

7. The memory system of claim 6 wherein the control circuitry further comprises a voltage reference circuit configured to produce a reference voltage, with the first, second and third comparator circuits each having a second input coupled to receive the reference voltage.

8. The memory system of claim 7 wherein the first, second and third intermediate voltages have a magnitude equal to a magnitude of the reference voltage.

9. The memory system of claim 1 wherein the voltage divider circuit comprises a first voltage divider circuit which comprises a first impedance coupled intermediate the programming voltage node and the third node, a second impedance coupled intermediate the third and second nodes, a third impedance coupled intermediate the first and second nodes, and a fourth impedance coupled intermediate the first node, and a second voltage divider circuit which comprises fifth, sixth, seventh and eighth impedances coupled in series, and wherein the voltage divider circuit further comprises switching circuitry configured to selectively couple a junction formed by the fifth and sixth impedances to the third node, a junction formed by the sixth and seventh impedances to the second node, and a junction formed by the seventh and eighth impedances to the first node when the voltage divider circuit is in the first state, and to decouple the junctions from the first, second and third nodes when the voltage divider circuit is in the second state.

10. A memory system comprising:

an array of memory cells;

a memory controller which controls memory operations on the array of memory cells, including memory program operations;

a programming voltage node configured to receive a programming voltage;

voltage sense circuitry, operably coupled to the programming voltage node and configured to sense a magnitude of the programming voltage;

program interrupt circuitry which causes the memory controller to terminate one of the memory programming operations should the programming voltage magnitude fall outside first or second separate programming voltage ranges;

wherein the voltage sense circuitry comprises a first resistor network, with the first resistor network comprising a plurality of resistors connected to form a voltage divider, with the first resistor network having a first node for coupling to the programming voltage node and a second node for coupling to a circuit common, a third node where a first divided voltage is produced when the programming voltage is at a lower limit of the first programming voltage range, and a fourth node where a second divided voltage is produced when the programming voltage is at a lower limit of the second programming voltage range.

11. The memory system of claim 10 wherein the voltage sense circuitry comprises a first comparator circuit having a first input coupled to the third node of the first resistor network and a second input coupled to a reference voltage.

12. The memory system of claim 11 wherein the voltage sense circuitry comprises a second comparator circuit having a first input coupled to the fourth node of the first resistor network and a second input coupled to the reference voltage.

13. The memory system of claim 12 wherein the first resistor network also has a fifth node where a divided voltage is produced when the programming voltage is at a higher limit of the second programming voltage range, and the voltage sense circuitry includes a third comparator circuit having a first input coupled to the fifth node of the first resistor network and a second input coupled to the reference voltage.

14. The memory system of claim 13 wherein the program interrupt circuitry comprises logic circuitry which logically combines outputs of the first, second and third comparator circuits.

15. The memory system of claim 10 wherein the voltage sense circuitry further comprises a second resistor network comprising a plurality of resistors connected to form a voltage divider and switching circuitry for connecting the second resistor network in parallel with the first resistor network and disconnecting the second resistor network from the first resistor network, with the first resistor network having a series resistance that is at least twice as great as a series resistance of the second resistor network.

16. A memory system, comprising:

an array of memory cells;

a memory controller which controls memory programming operations of the memory system;

a programming voltage node configured to receive a first programming voltage;

a voltage divider circuit operably coupled to the programming voltage node and the memory controller, the voltage divider circuit switchable between a first state in which the voltage divider circuit produces signals to initiate programming if the first programming voltage is within one of a first plurality of voltage ranges, and a second state in which the voltage divider circuit produces signals to continue programming if the first programming voltage is within one of a second plurality of voltage ranges.

17. The memory system of claim 16, wherein the first plurality of voltage ranges comprises:

a first voltage range having a first upper limit and a first lower limit; and

a second voltage range having a second upper limit and a second lower limit, the second upper limit having a voltage level magnitude less than the first lower limit.

18. The memory system of claim 17, wherein the second plurality of voltage ranges comprises:

a third voltage range having the first upper limit and a third lower limit having a magnitude less than the first lower limit; and

a fourth voltage range having the second upper limit and a fourth lower limit having a magnitude less than the second lower limit.

19. The memory system of claim 16 wherein the voltage divider circuit consumes more electrical power in the first state than in the second state.

20. The memory system of claim 16 wherein the voltage divider circuit consumes an order of magnitude more electrical power in the first state than in the second state.

21. A memory system, comprising:

an array of memory cells;

a memory controller which controls memory programming operations for the memory system;

a programming voltage node configured to receive a first programming voltage; and

a voltage detection circuit, comprising;

a voltage divider circuit operably coupled to the programming voltage node, the voltage detection circuit to detect when the first programming voltage is at a first voltage level and to produce a first intermediate voltage at a first node in response thereto, and to detect when the first programming voltage moves to a second voltage level and to produce a second intermediate voltage at a second node when the first programming voltage reaches the second voltage level.

22. The memory system of claim 21, wherein the first voltage level is at a lower end of a first voltage range, and the second voltage level is at the top of a second voltage range.

23. The memory system of claim 22, wherein the first voltage range has an upper limit and a lower limit, and the second voltage range has an upper limit and a lower limit, and wherein the lower limit of the first voltage range is at a higher potential than the upper limit of the second voltage range.

24. The memory system of claim 21, and further comprising:

a first comparator having a first input coupled to the first node; and

a second comparator having a first input coupled to the second node.

25. A memory system, comprising:

an array of memory cells;

a memory controller which controls memory programming operations of the memory system;

a programming voltage node configured to receive a first programming voltage; and

a voltage divider circuit operably coupled to the programming voltage node, the voltage divider circuit to detect when the first programming voltage is at a first voltage level and to produce a first intermediate voltage at a first node in response thereto, and to detect when the first programming voltage moves to a second voltage level and to produce a second intermediate voltage at a second node when the first programming voltage reaches the second voltage level;

a first comparator having a first input coupled to the first node; and

a second comparator having a first input coupled to the second node.

26. The memory system of claim 25, wherein the voltage divider circuit is further configured to produce a third intermediate voltage at a third node, the voltage divider circuit further comprising:

a third comparator having a first input coupled to the third node.

27. The memory system of claim 26, wherein the voltage divider circuit further includes combinational logic circuitry operably coupled to outputs of the first, second, and third comparators and to the memory controller to inhibit the memory controller from initiating programming operations if the first programming voltage at the first node is below the first voltage level or above the second voltage level.

28. The memory system of claim 26, wherein the first voltage level is at a lower limit of a first voltage range, and wherein the second voltage level is at an upper limit of a second voltage range.