Distributed signal drivers in arrayable devices

• US 6,256,233 B1
• Filed: 06/07/1995
• Issued: 07/03/2001
• Est. Priority Date: 07/26/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Glass, Richard J.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/474,856
• Time in Patent Office: 2,218 Days
• Field of Search: 365/189.05, 365/230.08
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Distributed buffering memory device (10) is provided which includes memory circuitry (12) located therein and independent buffering circuitry (16). Device (10) can be used in an array of devices where buffering circuitry (16) is employed to buffer the signals necessary for the array. Each independent buffer is employed to buffer a signal and supply that signal to a bank unique input bus which is used to drive the inputs of the array.

Claims

1. A device for use in an array of microcircuit devices, said array of devices having distributed buffering of control signals, each device requiring buffered control signals to be applied thereto, said array further including a network for distribution of said buffered control signals to said array of devices, each of said devices comprising:

functional circuitry for processing signals applied thereto; and

a buffer circuit functionally independent from and residing on the same microcircuit as said functional circuitry, wherein each buffer circuit buffers one of a plurality of control signals, each said one buffered control signal being applied to said network for distribution to functional circuitry of devices of said array.

2. The device of claim 1, further comprising a pull-up resistor operable to isolate said buffer circuit when said buffer circuit is not connected in said system.

3. The device of claim 1, wherein said functional circuitry is memory circuitry.

4. The device of claim 3, wherein said functional circuitry is DRAM circuitry.

5. The device of claim 3, wherein said functional circuitry is SRAM circuitry.

6. The device of claim 3, wherein said functional circuitry is ROM circuitry.

7. The device of claim 3, wherein said functional circuitry is PROM circuitry.

8. A system with distributed buffering, comprising:

an array of devices organized into a plurality of banks and coupled to a plurality of control signals, each of said devices operable to perform a signal processing function with functional circuitry;

each of said devices further including a buffering circuit functionally independent from and residing on the same microcircuit as said functional circuitry, said buffering circuit operable to buffer a one of said control signals; and

a bank input bus associated with each of said banks, wherein said buffered control signals are applied to said bank input bus, said bank input bus distributing said buffered control signals to functional circuitry of said devices within said bank to control the function of said devices.

9. The system of claim 8, wherein said devices further include a pull-up resistor operable to isolate said buffering circuit when said buffering circuit is not connected in said system.

10. The system of claim 8, wherein said devices are memory devices.

11. The system of claim 10, wherein said functional devices are DRAMs.

12. The system of claim 10, wherein said functional devices are SRAMs.

13. The system of claim 10, wherein said functional devices are ROMs.

14. The system of claim 10, wherein said functional devices are PROMs.

15. a system for distributing a plurality of buffered signals to functional circuitry of said system, said system comprising:

an array of devices, each device processing signals applied thereto; and

a buffer circuit functionally independent of said device function circuit, said buffer circuit buffering signals applied thereto;

a first network for distributing each of a plurality of input signals to an associated device buffer circuit; and

a second network having buffered signals from each associated device buffer circuit applied thereto, said second network distributing buffered signals to preselected device functional circuits;

wherein said device further includes a pull-up resistor operable to isolate said buffer circuit when said buffer circuit is not connected in the system.