Dual clocks for network device

• US 6,256,320 B1
• Filed: 05/29/1998
• Issued: 07/03/2001
• Est. Priority Date: 05/01/1998
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Tang, Wen-Tsung, Wadhawan, Ruchi
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US09/087,104
• Time in Patent Office: 1,131 Days
• Field of Search: 370/462, 370/276, 370/285, 370/293, 370/327, 370/340, 370/352, 370/353, 370/359, 370/360, 370/367, 370/391, 370/396, 370/398, 370/400, 370/401, 370/402, 370/406, 370/419, 370/422, 370/279, 370/356, 370/357, 370/364, 370/365
• US Class Current: 370/462
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A distributed arbitration scheme for a network. Ports in a network device determine which port in a set of ports may broadcast a packet onto a bus in the network device. A method of transmitting data between a set of ports sharing a bus in hub is described. The set of ports includes a first port, and the method comprises the first port receiving a packet, the first port requesting the bus, and, if another port is requesting the bus, the first port transmitting the packet to the bus if the first port has not transmitted a packet later than the another port requesting the bus. A system using two clocks of different speeds in a network device. The hub has at least a port. The port has an internal data path having a first width. A bus is coupled to the port. The bus has a data path that has a second width. The second width is greater than the first width. The hub includes a first clock that has a first frequency and is coupled to circuitry in the port for clocking internal data transfers. The hub includes a second clock that has a second frequency less than the first frequency, and the second clock is coupled to circuitry in the port for qualifying data transfers with the bus.

Claims

1. A hub comprising:

at least a port, the port having an internal data path having a first width;

a bus coupled to the port, the bus having a data path having a second width, wherein the second width is greater than the first width;

a first clock having a first frequency, the first clock coupled to circuitry in the port for clocking internal data transfers; and

a second clock having a second frequency less than the first frequency and at least 30 MHz, a ratio between the second frequency and the first frequency being equal to a ratio between the first width and the second width, the second clock coupled to circuitry in the port for controlling timing of data transfers with the bus.

2. The hub of claim 1, the second clock comprising the first clock divided.

3. The hub of claim 1, the second clock phase locked with the first clock.

4. The hub of claim 1, the first width comprising 16 bits.

5. The hub of claim 1, the second width comprising 32 bits.

6. The hub of claim 1, the second width comprising a number in the range of 32 to 128 bits.

7. The hub of claim 1, the first frequency comprising about 63 MHz.

8. The hub of claim 1, the second frequency comprising about 31 MHz.

9. The hub of claim 1, the second frequency comprising a number in the range of 30 to 70 MHz.

10. The hub of claim 1, the hub transmitting data greater than 1 Gigabits per second.

11. The hub of claim 1, the hub transmitting data greater than 2 Gigabits per second.

12. The hub of claim 1, the hub transmitting data less than 3 Gigabits per second.

13. The hub of claim 1, the hub transmitting data greater than 2 Gigabits per second and less than 3 Gigabits per second.

14. The hub of claim 1, including a plurality of ports coupled to the first clock and the second clock, a skew between the first clock received at a first port in the plurality of ports and the first clock received at any other port in the plurality of ports comprising less than one nanosecond.

15. The hub of claim 1, including a plurality of ports coupled to the first clock and the second clock, a skew between the first clock received at a first port in the plurality of ports and the first clock received at any other port in the plurality of ports comprising less than 500 picoseconds.

16. The hub of claim 1, including a plurality of ports coupled to the first clock and the second clock, a skew between the second clock received at a first port in the plurality of ports and the second clock received at any other port in the plurality of ports comprising less than one nanosecond.

17. The hub of claim 1, including a plurality of ports coupled to the first clock and the second clock, a skew between the second clock received at a first port in the plurality of ports and the second clock received at any other port in the plurality of ports comprising less than 500 picoseconds.

18. The hub of claim 1, data having a delay from transmission on the bus to receipt at a port of less than a period of the second clock.

19. The hub of claim 1, wherein the first clock is coupled to the circuitry in the port for clocking data transfers with the bus, for clocking data transfers with the bus in conjunction with the second clock.

20. The hub of claim 1, wherein the second clock has a state during which data transfers from the bus to the port are clocked, the state beginning at a time sufficiently long enough after data is clocked from a source to allow the data to be stable at the port at a leading edge of the first clock during the state.

21. The hub of claim 1, wherein data transfers from a source to the bus are clocked during a first state of the second clock and data transfers from the bus to the port are clocked during reoccurrence of the first state after a second state.

22. The hub of claim 21, wherein the first state corresponds to a low level of the second clock and the second state corresponds to a high level of the second clock.

23. The hub of claim 1, wherein the second clock has a state during which data transfers from the bus to the port are clocked, a delay exists from data being clocked from a source to data being received at the port, and the delay is sufficient to allow the data to be stable at the port at leading edge of the first clock during the state.

24. The hub of claim 1, the first clock coupled other than via the bus to the circuitry in the port for clocking internal data transfers.

25. The hub of claim 1, the second clock coupled other than via the bus to the circuitry for clocking data transfers with the bus.

26. A full duplex Ethernet hub comprising:

a plurality of ports coupled to a bus, the ports and bus each having a data path having a data a first clock coupled to a port in the plurality of ports, the first clock having a first frequency;

a second clock coupled to the port, the second clock having a second frequency, the second frequency being lower than the first frequency and at least 30 MHz, a ratio between the second frequency and the first frequency being equal to a ratio between the data width of the ports and the data width of the bus; and

logic to clock data into the port based on a state of the first clock and a state of the second clock.

27. The Ethernet hub of claim 26, including logic to clock data out of a second port in the plurality of ports based on the first clock and the second clock.

28. The Ethernet hub of claim 26 the second clock comprising the first clock divided.

29. The Ethernet hub of claim 26 the second clock phase locked with the first clock.

30. The Ethernet hub of claim 26 the first frequency comprising about 63 MHz and the second frequency comprising about 31 MHz.

31. The Ethernet hub of claim 26, the hub transmitting data greater than 2 Gigabits per second and less than 3 Gigabits per second.

32. The Ethernet hub of claim 26, the bus having a delay from transmission on the bus to receipt at a port of less than a period of the second clock.

33. The Ethernet hub of claim 26, comprising a first plurality of clocks including the first clock, clocks in the first plurality of clocks coupled to circuitry in respective ports for clocking internal data transfers in the respective ports.

34. The Ethernet hub of claim 33, clocks in the first plurality of clocks phase locked with each other.

35. The Ethernet hub of claim 33, comprising a second plurality of clocks including the second clock, clocks in the second plurality of clocks coupled to circuitry in respective ports for clocking data transfers with the bus.

36. The Ethernet hub of claim 35, clocks in the second plurality of clocks phase locked with each other.

37. The Ethernet hub of claim 26, ports in the plurality of ports coupled to the first clock and the second clock, a skew between the first clock received at a first port in the plurality of ports and the first clock received at any other port in the plurality of ports comprising less than one nanosecond.

38. The Ethernet hub of claim 26, ports in the plurality of ports coupled to the first clock and the second clock, a skew between the first clock received at a first port in the plurality of ports and the first clock received at any other port in the plurality of ports comprising less than 500 picoseconds.

39. The Ethernet hub of claim 26, ports in the plurality of ports coupled to the first clock and the second clock, a skew between the second clock received at a first port in the plurality of ports and the second clock received at any other port in the plurality of ports comprising less than one nanosecond.

40. The Ethernet hub of claim 26, ports in the plurality of ports coupled to the first clock and the second clock, a skew between the second clock received at a first port in the plurality of ports and the second clock received at any other port in the plurality of ports comprising less than 500 picoseconds.

41. A method of transferring data in a network device having a bus and at least a circuit coupled to the bus, the method comprising:

clocking data within the circuit with a first signal having a first frequency, the first signal provided other than via the bus; and

clocking data into the circuit with a second signal having a second frequency, the second signal provided other than via the bus;

wherein the second frequency being at least 30 MHz and a ratio between the second frequency and the first frequency being equal to a ratio between a data width of a device from which the data is transmitted and a data width of the bus.

42. The method of claim 41, the method comprising clocking the data into the circuit with the first signal and the second signal.

43. The method of claim 41, the method comprising clocking the data into the circuit with the second leading edge of the first signal after a leading edge of the first signal at which the data was clocked out of a source.

44. The method of claim 41, the method comprising clocking the data into the circuit with the leading edge of the first signal and a second half of a cycle of the second signal.

45. The method of claim 41, the method comprising clocking data from a second circuit onto the bus with the first signal and the second signal.