Transmission apparatus for half duplex communication using HDLC

• US 6,256,325 B1
• Filed: 06/03/1998
• Issued: 07/03/2001
• Est. Priority Date: 06/04/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Chan-Sik
• Primary Examiner(s): Marcelo, Melvin
• Assistant Examiner(s): KWOH, JASPER C
• Application Number:
  US09/089,763
• Time in Patent Office: 1,126 Days
• Field of Search: 370/503, 370/509, 370/511, 370/513, 370/514, 340/928, 340/933, 340/942, 235/375, 235/380, 235/381, 235/384
• US Class Current: 370/503
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A transmission apparatus for half duplex communication using HDLC is provided, in which a simple logic circuit is added to a general HDLC controller to transmit a frame, adding flags before and after the frame all the time, without modification of program even when a transmission speed is changed, thereby enabling rapid and reliable communications. The transmission apparatus for half duplex communication using HDLC includes: a clock (TxC) generator, to supply it to each section of the apparatus as a synchronous clock; an HDLC controller for outputting a flag signal in a predetermined bit pattern while it does not transmit a frame signal; flag delay/detecter for outputting with delaying an output (TxD) of the HDLC controller by one byte, and outputting a flag detection signal (/Flag_detect) whenever the flag signal is detected; a CPU for outputting a transmission request signal (/Tx_Req) during a period determined with relation to the magnitude of the frame signal when data transmission is required, and sending the frame signal to the HDLC controller after a transmission ready signal (/Tx_Ready) is received; control logic for synchronizing the transmission request signal (/Tx_Req) with the flag detection signal (/Flag_detect) subsequently generated, to generate the transmission ready signal (/Tx_Ready), and to output a transmission enable signal (/Tx_Enable) determining a transmission enable time, thereby adding a desired number of flag signals (Flag) before and after the frame signal; and an output controller for sequentially encoding signals output from the HDLC controller in a predetermined code system, and outputting the encoded signals during an active time of the transmission enable signal (/Tx_Enable).

Claims

1. A transmission apparatus for half duplex communication using high level data link control (HDLC), comprising:

means for generating a clock signal, to supply the clock signal to each section of the apparatus as a synchronous clock signal;

an HDLC controller for outputting an output signal via an output terminal, said output signal comprising a flag signal and a frame signal, said flag signal being repeatedly output except when said frame signal is output;

flag delay/detection means for delaying said output signal of said HDLC controller by one byte, and outputting a flag detection signal whenever said flag signal is detected;

a central processing unit for outputting a transmission request signal when data transmission is required, and for sending said frame signal to said HDLC controller after a transmission ready signal is received;

control logic means for synchronizing said transmission request signal with said flag detection signal to generate said transmission ready signal, and for generating a delayed transmission ready signal and outputting a transmission enable signal determining a transmission enable time, in response to said transmission ready signal and said delayed transmission ready signal, to enable a desired number of flag signals to be transmitted before and after said frame signal; and

output control means for sequentially encoding signals output from said HDLC controller via said flag delay/detection means according to a predetermined code system, and outputting the encoded signals during an active time of said transmission enable signal.

2. The transmission apparatus as claimed in claim 1, wherein said flag delay/detection means comprise:

an 8-bit shift register responsive to said clock signal for receiving the output signal from said HDLC controller and outputting a delayed output signal; and

an 8-bit comparator for comparing the contents of said 8-bit shift register to a predetermined flag pattern, said 8-bit comparator generating said flag detection signal when said contents of said 8-bit shift register correspond to said flag pattern.

3. The transmission apparatus as claimed in claim 1, wherein said control logic means comprise:

a first D type flip-flop having a data input connected to said central processing unit for receiving said transmission request signal, a clock input for receiving said flag detection signal, and an output for outputting said transmission ready signal;

a second D type flip-flop having a data input for receiving said transmission ready signal output from said first D type flip-flop, a clock input for receiving said flag detection signal and an output for outputting said delayed transmission ready signal by a time period corresponding to one flag period; and

an AND-gate for receiving said transmission ready signal and said delayed transmission ready signal to generate said transmission enable signal.

4. The transmission apparatus as claimed in claim 2, wherein said control logic means comprise:

a first D type flip-flop having a data input connected to said central processing unit for receiving said transmission request signal, a clock input for receiving said flag detection signal s output by said 8-bit comparator, and an output for outputting said transmission ready signal;

a second D type flip-flop having a data input for receiving said transmission ready signal output from said first D type flip-flop, a clock input for receiving said flag detection signal output by said 8-bit comparator, and an output for outputting said delayed transmission ready signal by a time period corresponding to one flag period; and

an AND-gate for receiving said transmission ready signal and said delayed transmission ready signal to generate said transmission enable signal.

5. The transmission apparatus as claimed in claim 1, wherein said output control means outputs only a carrier signal when there is no frame signal to be transmitted.

6. The transmission apparatus as claimed in claim 1, wherein said output control means comprise:

an encoding logic for coding said signals output from said HDLC controller via said flag delay/detection means in a Manchester code or FM0 code;

a negative-logic tri-state buffer for passing a transmission signal encoded by encoding logic only while said transmission enable signal is at a low logic level; and

a positive-logic tri-state buffer for passing a high-level logic signal while said transmission enable signal is at a high logic level.

7. The transmission apparatus as claimed in claim 2, wherein said output control means comprise:

an encoding logic for coding said signals output from said HDLC controller via said flag delay/detection means in a Manchester code or FM0 code;

a negative-logic tri-state buffer for passing a transmission signal encoded by encoding logic only while said transmission enable signal is at a low logic level; and

a positive-logic tri-state buffer for passing a high-level logic signal while said transmission enable signal is at a high logic level.

8. The transmission apparatus as claimed in claim 4, wherein said output control means comprise:

an encoding logic for coding said signals output from said HDLC controller via said flag delay/detection means in a Manchester code or FM0 code;

a negative-logic tri-state buffer for passing a transmission signal encoded by encoding logic only while said transmission enable signal is at a low logic level; and

a positive-logic tri-state buffer for passing a high-level logic signal while said transmission enable signal is at a high logic level.

9. The transmission apparatus as claimed in claim 5, wherein said output control means comprise:

an encoding logic for coding said signals output from said HDLC controller via said flag delay/detection means in a Manchester code or FM0 code;

a negative-logic tri-state buffer for passing a transmission signal encoded by encoding logic only while said transmission enable signal is at a low logic level; and

a positive-logic tri-state buffer for passing a high-level logic signal while said transmission enable signal is at a high logic level, said output control means outputting said carrier signal in response to said high-level logic signal.

10. A method of data transmission for half duplex communication using high level data link control (HDLC), comprising:

repeatedly generating a flag signal from an HDLC controller;

delaying said flag signal by one flag period;

comparing said delayed flag signal to a predetermined flag pattern and generating a flag detection signal when said delayed flag signal correspond to said flag pattern;

generating a transmission request signal when data transmission is required;

generating a transmission ready signal by synchronizing said transmission request signal with said flag detection signal;

outputting a frame signal in response to said transmission ready signal;

generating a delayed transmission ready signal by delaying said transmission ready signal;

logically combining said transmission ready signal and said delayed transmission ready signal to generate a transmission enable signal having a predetermined period for enabling a desired number of said flag signals to be added before and after said frame signal; and

encoding said frame signal and said flag signals added before and after said frame signal, according to a predetermined code system, for transmission.

11. The method as set forth in claim 10, wherein said step of encoding comprises encoding according to a Manchester code.

12. The method as set forth in claim 10, wherein said step of encoding comprises encoding according to a FM0 code.

13. The method as set forth in claim 10, wherein said step of generating a transmission request signal comprises generating said until a predetermined time after completing the outputting of said frame signal.

14. The method as set forth in claim 13, wherein said predetermined time corresponds to one flag period.