D.T.R.M. data timing recovery module

• US 6,256,361 B1
• Filed: 07/23/1999
• Issued: 07/03/2001
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Mozetic, Carlo, Testa, Francesco
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/171,844
• Time in Patent Office: 711 Days
• Field of Search: 375/354, 375/359, 375/360, 375/373, 375/376, 327/141, 327/155, 327/159, 331/25
• US Class Current: 375/360
• CPC Class Codes: H03B 5/1203 the amplifier being a single transistor
• CPC Class Codes: H03B 5/1231 the amplifier comprising one or more bipolar transistors
• CPC Class Codes: H03B 5/1256 the means comprising a variable inductance
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A data timing recovery system for clock recovery based on a pulse generator circuit and an injection locked oscillator ILO, which extracts the clock signal at high rate and preserves the timing information during long “0” or “1” sequences. This system may also include a clock extractor circuit including the ILO, a phase aligner circuit and a clock killer circuit. Connections to and from the system are an incoming data link, an outgoing data link, an outgoing clock link, an enable/disable link and a loss of signal data link. A data link connected between the pulse generator circuit and the phase aligner circuit and to the clock killer circuit. A pulse link connected to the ILO. A recovered clock link connected between the clock extractor circuit and the phase aligner circuit.

Claims

1. A data timing recovery system for clock recovery comprising:

a pulse generator circuit; and

an injection locked oscillator, the system being connected to an incoming data link and an outgoing clock link wherein the pulse generator circuit further comprises;

a zero crossing circuit; and

a differential splitter, being connected with the zero crossing circuit, the differential splitter being connected to the incoming data link, and the zero crossing circuit being connected with a pulse link to the injection locked oscillator where the pulse generator circuit generates a pulse at every data transition event to form a flow of pulses to the injection locked oscillator that utilizes the pulses to phase lock a frequency and is also connected to the outgoing link that is sending out a first recovered clock.

2. The data timing recovery system of claim 1 wherein the differential splitter is connected to a second data link.

3. The data timing recovery system of claim 2 wherein a phase aligner circuit is connected to a clock extractor via a recovered clock link and to the pulse generator circuit via the second data link and to an outgoing data link.

4. The data timing recovery system of claim 2 further comprising a clock killer circuit connected to the pulse generator circuit via the second data link and to a loss of signal link.

5. The data timing recovery system of claim 1 further comprising:

a clock extractor including the injection locked oscillator; and

a clock extractor buffer being connected to the oscillator by a recovered clock link wherein the clock extractor buffer is connected to the outgoing clock link.

6. The data timing recovery system of claim 5 wherein the clock extractor buffer is connected to an enable/disable link.

7. A method for clock recovery in a data timing recovery system having a pulse generator stage and a clock extractor stage comprising the steps of:

the pulse generator stage receiving incoming data, generating pulses at every data transition event, dividing the incoming data to pulses and to data, sending the data to a phase aligner stage and the pulses to the clock extractor stage; and

the clock extractor stage receiving the pulses from the pulse generator stage, recovering a second recovered clock signal with the help of the pulses, and sending out a first recovered clock to an outgoing clock link.

8. The method of claim 7 further comprising the steps of the pulse generator stage sending the data to a clock killer stage.

9. The method of claim 8 further comprising the steps of:

the clock killer stage, when receiving the data from the pulse generator stage, sending out a data loss signal ON on a loss of signal link.

10. The method of claim 8 further comprising the steps of:

the clock killer stage, when not receiving the data from the pulse generator stage, setting an alarm, sending out a data loss signal OFF on a loss of signal link.

11. The method of claim 7 further comprising the steps of the clock extractor stage distributing the second recovered clock to the phase aligner stage.

12. The method of claim 11 further comprising the steps of:

the clock extractor stage turning off the sending of the second recovered clock to the phase aligner stage.

13. The method of claim 11 further comprising the steps of:

the clock extractor stage turning on the sending of the second recovered clock to the phase aligner stage.

14. The method of claim 7 further comprises the steps of:

the phase aligner stage receiving the data from the pulse generator stage, receiving the second recovered clock from the clock extractor stage, aligning the data and the second recovered clock resulting in phase aligned data; and

sending out the phase aligned data on an outgoing data link.

15. The method of claim 7 comprising the further steps of:

the clock extractor stage, being a switching off sequence, receiving an external clock disable signal OFF on a external enable/disable link;

the clock extractor stage switching a clock extractor buffer to disable mode, closing the clock extractor buffer, turning OFF the clock extractor buffer whereby the sending of first recovered clock being turned off from the outgoing clock link.

16. The method of claim 7 further comprising the steps of:

the clock extractor stage, being a switching on sequence, receiving an external clock disable signal ON on a external enable/disable link, switching the clock extractor buffer to normal mode, opening the clock extractor buffer, turning ON the clock extractor buffer thereby initiating sending of the first recovered clock being turned on from the outgoing clock link.