Reliable interrupt reception over buffered bus

• US 6,256,699 B1
• Filed: 12/15/1998
• Issued: 07/03/2001
• Est. Priority Date: 12/15/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Lee, Glenn E.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/212,016
• Time in Patent Office: 931 Days
• Field of Search: 710/126-128, 710/107, 710/260-269
• US Class Current: 710/310
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A method and apparatus for reliable interrupt reception over a buffered bus utilizes a mailbox register to receive interrupt request information sent after a data write transaction. The data is sent from an initiating peripheral device over the buffered bus to arrive with an arbitrary delay at the host memory. After completing the sending phase for the data the initiating peripheral device sends a mailbox register data block containing an interrupt request to a mailbox register associated with the host processor. Because the mailbox register data block will necessarily arrive after the receipt of the actual data in the host memory because it is following the actual data through the same buffered bus, the interrupt will be properly sequenced with the receipt of data.

Claims

1. A method for sending data from an initiating device to a host processor coupled to a host memory and a mailbox register, said method comprising:

transmitting the data over a buffered bus from the initiating device to the host memory;

buffering the data transmission between the initiating device and the host memory;

issuing an interrupt request over the buffered bus from the initiating device to the mailbox register so as to set a corresponding location in the mailbox register corresponding to the initiating device to indicate a pending interrupt request from the corresponding initiating device, said issuing the interrupt request occurring after said transmitting the data over the buffered bus is complete;

reading the contents of the corresponding location with the host processor;

detecting an interrupt when said corresponding location is set to indicate a corresponding pending interrupt request; and

processing the data in the host memory in response to detecting the interrupt request.

2. A method in accordance with claim 1, further comprising:

responding to said interrupt request.

3. A method in accordance with claim 2 wherein said responding includes resetting the contents of the corresponding location within the mailbox register.

4. A method in accordance with claim 2 wherein said responding includes signaling the initiating device.

5. A method in accordance with claim 3, further comprising:

reading with the initiating device the reset contents of the corresponding location within the mailbox register.

6. An apparatus for communicating data from a first plurality of initiating devices, comprising:

a buffered bus in communication with the first plurality of initiating devices;

a host memory in communication with the buffered bus;

a mailbox register having a second plurality of memory locations, said mailbox register in communication with said buffered bus, wherein each particular memory location corresponds to a particular initiating device; and

a host processor in communication with said host memory and said mailbox register, said host processor having a third plurality of interrupt inputs, each particular interrupt input corresponds to a particular memory location, wherein each particular memory location is responsive to an interrupt request signal from a corresponding particular initiating device to indicate that an interrupt request has been issued by the device to said host processor, and wherein the interrupt request signal is issued over said buffered bus after said data is transmitted over said buffered bus.

7. An apparatus according to claim 6 wherein said host processor reads the data from said host memory in response to receiving said interrupt request.

8. An apparatus according to claim 7 wherein said host processor processes the data read from said host memory.

9. An apparatus according to claim 8 wherein said host processor signals the initiating device in response to receiving said interrupt request.

10. An apparatus according to claim 8 wherein said host processor resets said interrupt request signal in response to receiving said interrupt request.

11. An apparatus according to claim 6 further comprising:

a bridge disposed in said buffered bus.

12. An apparatus according to claim 11 where said bridge supports posted write transactions and the indicating devices use posted write transactions to communicate the data over said buffered bus.

13. An apparatus according to claim 12 wherein the initiating devices use posted write transactions to communicate mailbox register contents over said buffered bus.