Method and apparatus for setting the operating parameters of a computer system

• US 6,256,731 B1
• Filed: 11/15/1999
• Issued: 07/03/2001
• Est. Priority Date: 01/02/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LeClerg, Frank E., Yuratovac, John, Kinion, Mike, Babcock, Sean R., Wildgrube, Frank L., Christeson, Orville H., Hall, Jerald N.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/440,150
• Time in Patent Office: 596 Days
• Field of Search: 713/1, 713/2, 713/100, 713/500, 713/501, 713/600
• US Class Current: 713/1
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.

Claims

1. A computer system comprising:

a configuration selector (CS) to selectively denote an of a plurality of computer system operating modes, said plurality of computer system operating modes comprising a configuration mode; and

a first plurality of configurable devices to be configured in response to the configuration mode being denoted by the configuration selector, the first plurality of configurable devices including

a storage medium having stored therein a plurality of instructions to implement a basic input/output system (BIOS) equipped to operate in each of the plurality of operating modes, wherein, in the configuration mode, the BIOS is to facilitate programming of a plurality of operating parameters for a second plurality of configurable devices,

a processor, coupled to the storage medium, to execute the BIOS, and

a programmable multiplexer to assert a default bus/core ratio common to the first and second plurality of configurable devices when in the configuration mode.

2. The computer system of claim 1, wherein the programmable multiplexer is to assert a programmed bus/core ratio when not in the configuration mode.

3. The computer system of claim 1, wherein the second plurality of configurable devices includes the processor.

4. The computer system of claim 1, wherein the second plurality of configurable devices includes a complementary metal oxide semiconductor (CMOS) memory device.

5. The computer system of claim 4, wherein the CMOS memory device has stored therein a plurality of extended system configuration data.

6. The computer system of claim 1, wherein the storage medium is a flash memory device.

7. A machine readable medium having stored thereon a plurality of machine executable instructions, execution of said plurality of machine executable instructions to implement a method comprising:

determining whether a configuration selector of a computer system denotes a configuration mode of operation;

asserting a default bus/core ratio common to a plurality of processors and buses comprising the computer system from a programmable multiplexer if the configuration selector denotes the configuration mode of operation;

executing a basic input/output system (BIOS) equipped to operate in the configuration mode of operation by a processor at a speed consistent with the asserted bus/core ratio, the processor being coupled to a bus that also operates at a speed consistent with the asserted bus/core ratio; and

facilitating user programming of the plurality of operating parameters by the BIOS operating in the configuration mode of operation.

8. A method comprising:

receiving from a configuration selector an indication of a mode of operation for a computer system, said configuration selector comprising a jumper block, and said mode of operation depending at least in part on a state of the jumper block;

asserting a programmed bus/core ratio if the configuration selector indicates a normal mode of operation; and

asserting a default bus/core ratio if the configuration selector indicates a configuration mode of operation, said default bus/core ratio comprising a bus/core ratio supported by a family of processors and buses that can be used in the computer system.

9. An apparatus comprising:

a configuration selector comprising a jumper block, said configuration selector to indicate a mode of operation for a computer system depending on a state of the jumper block; and

a programmable multiplexer to assert a programmed bus/core ratio if the configuration selector indicates a normal mode of operation, and to assert a default bus/core ratio if the configuration selector indicates a configuration mode of operation, said default bus/core ratio comprising a bus/core ratio supported by a family of processors and buses that can be used in the computer system.