Memory system having internal state monitoring circuit

• US 6,256,754 B1
• Filed: 06/15/1998
• Issued: 07/03/2001
• Est. Priority Date: 07/28/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/097,470
• Time in Patent Office: 1,114 Days
• Field of Search: 714/718, 714/719, 714/721, 714/724, 714/735, 714/736, 365/201, 324/158.1
• US Class Current: 714/718
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory system having a test mode which can be used to access signals internally generated by the system during its operation. The signals accessible in the test mode are not available to a standard user of the system, but can be used by a memory chip designer to determine the cause of a device failure. The memory system includes a test signal switch which is used to route one of a multitude of internal signals to an input/output (I/O) pad where the information can be accessed by a chip designer. In order to access the internal signals, the memory system is first placed into a test mode, which acts to shut off the data paths used for reading the output of the sense amplifier included as part of the data read path or for reading the contents of the status register. A signal specifying a particular test signal of interest is then input. Decode logic is used to verify the coded input signal and control the multiplexer to route a specified internal signal through the switch to the I/O pad. By operating the memory system and monitoring the selected signal or data, a chip designer can isolate the cause of a device failure and investigate solutions to the problem without the need for micro-probing of the device.

Claims

1. A memory device, comprising:

at least one pin;

an array of memory cells;

a state machine communicatively coupled to the array that generates signals to control read, write and erasure of data in the array;

a mode detector that detects a signal indicative of a selected mode of operation of the memory device; and

a switch responsive to the mode detector that routes at least one selected internal signal associated with at least one of the array and the state machine to the at least one pin of the memory device in real time for monitoring the at least one selected internal signal when the mode detector detects a signal that indicates a first mode of operation.

2. The memory device of claim 1, wherein the at least one selected internal signal comprises a signal that indicates the status of the state machine.

3. The memory device of claim 1, wherein the at least one selected internal signal comprises a signal that causes the state machine to transition from one state to another.

4. The memory device of claim 1, wherein the switch comprises a mutliplexer.

5. The memory device of claim 1, wherein the signal indicative of a selected mode comprises a high voltage which exceeds a predetermined level and wherein the selected mode of operation comprises a test mode.

6. The memory device of claim 1, wherein the signal indicative of a selected mode comprises two signals which each exceed a predetermined level.

7. The memory device of claim 1, wherein the at least one internal signal is either analog or digital test signals.

8. The memory device of claim 1, wherein the at least one internal signal is generated by the state machine during data read, data write, and data erase operations.

9. The memory device of claim 1, wherein the at least one internal signal is selected from a preprogram signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, or a maximum pulse allowed signal, all acquired during a standard memory erase operation.

10. A method of real time monitoring operating signals in a memory device, the method comprising:

performing a data processing operation on the memory device;

selecting at least one internal signal within the memory device during the data processing operation;

coupling the selected internal signal to an external connection of the memory device while the memory device performs the data processing operation; and

monitoring the internal signal.

11. The method of claim 10, wherein the data processing operation is a memory cell erase operation.

12. The method of claim 10, wherein selecting at least one internal signal comprises selecting at least one of a preprogram signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, and a maximum pulse allowed signal.

13. A method of testing a memory device, comprising:

initiating a first mode of operation of the memory device;

performing a memory operation during the first mode; and

selectively outputting internal signals, in real time, from the memory device generated during performance of the memory operation.

14. The method of claim 13, and further comprising selecting one of a data program, data read and data erase operation for the memory operation of the memory device.

15. The method of claim 13, wherein initiating a first mode of operation comprises initiating a test mode using an externally provided signal.

16. The method of claim 15, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level.

17. The method of claim 13, wherein selectively outputting comprises:

selecting one of the internal signals to be output on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the memory operation.

18. The method of claim 13, wherein the internal signals are either digital or analog signals.

19. The method of claim 13, wherein initiating a first mode of operation comprises initiating a test mode using a plurality of externally provided signals provided on a plurality of external connections.

20. The method of claim 13, wherein wherein initiating a first mode of operation comprises initiating a test mode by detecting a voltage provided on an external address connection which exceeds a predetermined voltage level.

21. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is to be routed to a data output means when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to a data input/output pad of the memory system when the test mode of operation is accessed.

22. The method of claim 21, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

23. The method of claim 22, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

24. The method of claim 21, wherein a plurality of test mode access signals are used to produce the test mode access state.

25. The method of claim 24, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

26. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is to be routed to a data output means when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to an address pin of the memory system when the test mode of operation is accessed.

27. The method of claim 26, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

28. The method of claim 27, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

29. The method of claim 26, wherein a plurality of test mode access signals are used to produce the test mode access state.

30. The method of claim 26, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

31. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation, wherein the test mode access state which allows entry to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is to be routed to a data output means when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to the data output means when the test mode of operation is accessed.

32. The method of claim 31, wherein a plurality of test mode access signals are used to produce the test mode access state.

33. The method of claim 31, wherein the selected signal is routed to a data input/output pad of the memory system.

34. The method of claim 31, wherein the selected signal is routed to an address pin of the memory system.

35. The method of claim 31, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

36. The method of claim 31, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

37. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a plurality of test mode access signals to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is to be routed to a data output means when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to the data output means when the test mode of operation is accessed.

38. The method of claim 37, wherein the test mode access state which allows entry to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

39. The method of claim 37, wherein the selected signal is routed to a data input/output pad of the memory system.

40. The method of claim 37, wherein the selected signal is routed to an address pin of the memory system.

41. The method of claim 37, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

42. The method of claim 37, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

43. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to a data input/output pad of the memory system in real time when the test mode of operation is accessed.

44. The method of claim 43, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

45. The method of claim 44, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

46. The method of claim 43, wherein a plurality of test mode access signals are used to produce the test mode access state.

47. The method of claim 43, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

48. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to an address pin of the memory system in real time when the test mode of operation is accessed.

49. The method of claim 48, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

50. The method of claim 49, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

51. The method of claim 48, wherein a plurality of test mode access signals are used to produce the test mode access state.

52. The method of claim 48, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

53. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation, wherein the test mode access state which allows entry to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to the data output node in real time when the test mode of operation is accessed.

54. The method of claim 53, wherein a plurality of test mode access signals are used to produce the test mode access state.

55. The method of claim 53, wherein the selected signal is routed to a data input/output pad of the memory system.

56. The method of claim 53, wherein the selected signal is routed to an address pin of the memory system.

57. The method of claim 53, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

58. The method of claim 53, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

59. A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising:

applying a plurality of test mode access signals to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation;

verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation;

selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed, wherein the internal signals include digital and analog signals; and

routing the selected signal to the data output node in real time when the test mode of operation is accessed.

60. The method of claim 59, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.

61. The method of claim 60, wherein verifying that the test mode access state produced is a valid one further comprises:

determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.

62. The method of claim 59, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.

63. A method of real time monitoring internal operating signals in a memory device, the method comprising:

externally providing a test mode initiation signal to the memory device;

initiating a test mode of operation of the memory device in response to a received test mode initiation signal;

performing a memory cell erase operation on the memory device;

selectively coupling an internal signal, during while performing a standard memory operation, to an external connection of the memory device in real time while the memory device is in the test mode; and

selecting at least one operation of a preprogram signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, and a maximum pulse allowed signal.

64. A method of real time monitoring operating signals in a memory device, the method comprising:

performing a memory cell erase operation on the memory device;

selecting at least one internal signal within the memory device during the data processing operation, wherein selecting at least one internal signal comprises selecting at least one of a preprogram signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, and a maximum pulse allowed signal;

coupling the selected internal signal to an external connection of the memory device while the memory device performs the data processing operation; and

monitoring the internal signal.

65. A method of testing a memory device, comprising:

initiating a first mode of operation of the memory device;

performing a memory operation during the first mode; and

selectively outputting internal signals, in real time, from the memory device generated during performance of the memory operation, wherein the internal signals are either digital or analog signals;

selecting one of the internals signal to be output, in real time, on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the memory operation.

66. The method of claim 65, and further comprising selecting one of a data program, data read and data erase operation for the memory operation of the memory device.

67. The method of claim 65, wherein initiating a first mode of operation comprises initiating a test mode using an externally provided signal.

68. The method of claim 67, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level.

69. The method of claim 65, wherein initiating a first mode of operation comprises initiating a test mode using a plurality of externally provided signals provided on a plurality of external connections.

70. The method of claim 65, wherein initiating a first mode of operation comprises initiating a test mode by detecting a voltage provided on an external address connection which exceeds a predetermined voltage level.

71. A method of testing a memory device, comprising:

initiating a test mode of operation using a plurality of externally provided signals provided on a plurality of external connections;

performing a memory operation during the first mode; and

selectively outputting internal signals, in real time, from the memory device generated during performance of the memory operation, wherein the internal signals are either digital or analog signals.

72. The method of claim 71, and further comprising selecting one of a data program, data read and data erase operation for the memory operation of the memory device.

73. The method of claim 71, wherein initiating a first mode of operation comprises initiating a test mode using an externally provided signal.

74. The method of claim 73, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level.

75. The method of claim 71, wherein selectively outputting comprises:

selecting one of the internal signals to be output on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the memory operation.

76. A method of testing a memory device, comprising:

initiating a test mode of operation of the memory device by detecting a voltage provided on an external address connection which exceeds a predetermined voltage level;

performing a memory operation during the first mode; and

selectively outputting internal signals, in real time, from the memory device generated during performance of the memory operation, wherein the internal signals are either digital or analog signals.

77. The method of claim 76, and further comprising selecting one of a data program, data read and data erase operation for the memory operation of the memory device.

78. The method of claim 76, wherein initiating a first mode of operation comprises initiating a test mode using an externally provided signal.

79. The method of claim 78, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level.

80. The method of claim 76, wherein selectively outputting comprises:

selecting one of the internal signals to be output on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the memory operation.

81. A method of testing a memory device, comprising:

initiating a test mode of operation of the memory device using an externally provided signal, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level;

performing a memory operation during the first mode; and

selectively outputting internal signals, in real time, from the memory device generated during performance of the memory operation;

selecting one of the internals signal to be output, in real time, on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the memory operation.

82. The method of claim 81, and further comprising selecting one of a data program, data read and data erase operation for the memory operation of the memory device.

83. The method of claim 81, wherein the internal signals are either digital or analog signals.

84. A method of testing an integrated memory device, comprising:

initiating a test mode of operation of the integrated memory device using a plurality of externally provided signals provided on a plurality of external connections;

selecting one of a data program, data read and data erase operation of the integrated memory device;

performing the selected operation during the test mode; and

selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.

selecting one of the internals signal to be output on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the selected operation.

85. The method of claim 84, wherein one of the externally provided signals is a voltage provided on an external connection which exceeds a predetermined voltage level.

86. The method of claim 84, wherein the internal signals are either digital or analog signals.

87. A method of testing an integrated memory device, comprising:

initiating a test mode of operation of the integrated memory device, wherein initiating a test mode comprises detecting a voltage provided on an external address connection which exceeds a predetermined voltage level;

selecting one of a data program, data read and data erase operation of the integrated memory device;

performing the selected operation during the test mode; and

selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.

selecting one of the internals signal to be output on an external connection; and

coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the selected operation.

88. The method of claim 87, wherein the internal signals are either digital or analog signals.

89. A method of testing an integrated memory device, comprising:

initiating a test mode of operation of the integrated memory device;

detecting a voltage provided on a first external connection which exceeds a predetermined voltage level;

selecting one of a data program, data read and data erase operation of the integrated memory device;

performing the selected operation during the test mode; and

selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.

selecting one of the internals signal to be output on a second external connection; and

coupling the one of the internal signals to the second external connection so that the one of the internal signals can be monitored in real time during the selected operation.

90. The method of claim 89, wherein initiating a test mode of operation further comprises:

latching a test mode code signal provided on a plurality of data input connections.

91. The method of claim 89, wherein the internal signals are either digital or analog signals.

92. A method of testing an integrated memory device, comprising:

initiating a test mode of operation of the integrated memory device, wherein initiating a test mode of operation comprises;

detecting a voltage provided on a first external connection which exceeds a predetermined level;

detecting a voltage provided on a second external connection which exceeds a predetermined level; and

latching a test mode code signal provided on a plurality of data input connections;

selecting one of a data program, data read and data erase operation of the integrated memory device;

performing the selected operation during the test mode; and

selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.

selecting one of the internals signal to be output on the first external connection; and

coupling the one of the internal signals to the first external connection so that the one of the internal signals can be monitored in real time during the selected operation.

93. The method of claim 92, wherein the internal signals are either digital or analog signals.

94. An integrated circuit memory device comprising:

test mode detection circuitry for detecting an externally provided test mode trigger and initiating a test mode in response to the test mode trigger;

output circuitry coupled to the test mode detection circuitry, wherein the output circuitry comprises a switching circuit comprises a multiplex circuit and wherein said output circuitry is configured to selectively output internal operating signals, in real time, acquired during standard memory operations in response to the initiated test mode; and

wherein the standard memory operations are performed during the test mode and comprise data read, data write, and data erase operations.

95. The integrated circuit memory device of claim 94, wherein the test mode detection circuitry is configured to monitor an external connection voltage for a high voltage which exceeds a predetermined level and to initiate a test mode in response to a detected high voltage.

96. The integrated circuit memory device of claim 94, wherein the test mode detection circuitry monitors two external connection voltages for high voltages which each exceed a predetermined level and initiates a test mode in response to two simultaneously detected high voltage on the two external connections.

97. The integrated circuit memory device of claim 94, wherein the switching circuit comprises a multiplex circuit.

98. The integrated circuit memory device of claim 94, wherein the internal operating signals are either analog or digital test signals.

99. The integrated circuit memory device of claim 94, wherein the internal operating signals are selected from a preprogram signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, or a maximum pulse allowed signal, all acquired during a standard memory erase operation.