Amoeba display for hierarchical layout

• US 6,256,768 B1
• Filed: 11/03/1998
• Issued: 07/03/2001
• Est. Priority Date: 11/03/1998
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Silicon Perspective Corporation
• Inventors: Igusa, Mitsuru
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/186,218
• Time in Patent Office: 973 Days
• Field of Search: 716/11, 716/1
• US Class Current: 716/124
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

CAD software for automated circuit design provides improved display of hierarchical layout. Component placement perimeters are shown with “amoeba” characteristic for improved circuit floor-planning and analysis. Amoeba view of hierarchical design perimeter enables more intuitive observation of circuit floor-plan from actual component placement. Informational brevity conveyed by perimeters of hierarchies in design facilitates simpler interpretation of complex circuit layout, as well as distributed data access to remote sites through email or low-speed network.

Claims

1. A method for processing a logic design defining an integrated circuit (IC) as a multiple level hierarchy of components formed by a plurality of cells, the method comprising the steps of:

a. processing said logic design to generate one of either a flat or a loose IC layout wherein cells of components of the IC are assigned to separate positions within an IC substrate;

b. analyzing said IC layout and the logic design to identify positions within said substrate to which cells forming each component of said hierarchy were assigned at step a; and

c. determining from the positions identified at step b, a shape and position of each of a plurality of areas of said layout, wherein each component of said multiple-level hierarchy corresponds to at least one area of said plurality of areas, and wherein each area of said plurality of areas has a perimeter sized and shaped to encompass those cells which are both included in the area'"'"'s corresponding component and which are contiguous to one another within said layout.

2. The method of claim 1 further comprising the step of:

d. displaying an amoeba-style drawing representing the layout, the drawing showing the perimeters of a subset of the plurality of areas determined at step c.

3. The method of claim 2 further comprising the step of:

e. selecting said subset of the plurality of areas whose perimeters are displayed at step d based on a number of cells included in each area.

4. The method of claim 2 further comprising the step of:

e. selecting said subset of the plurality of areas whose perimeters are displayed at step d based on the level of said hierarchy upon which each area'"'"'s corresponding component resides.

5. A method for processing a design describing a hierarchy of components, wherein each component is assigned to a level of a multiple level hierarchy, and wherein each component is formed by a plurality of cells, the method comprising the steps of:

a. generating a graphic design depicting a layout of all cells forming components of said hierarchy;

b. receiving the graphic design; and

c. determining from the graphic design a perimeter of areas of said layout bounding clusters of cells forming each component associated with such hierarchy; and

d. generating a representation of at least one amoeba-style drawing corresponding to the graphic design, wherein such drawing shows one or more perimeters associated with one or more components of said hierarchy.

6. The method of claim 5 further comprising the step of:

e. selecting each perimeter to be displayed in said drawing according to a number of cells bounded by the perimeter.

7. The method of claim 5 further comprising the step of

e. selecting each perimeter to be displayed in said drawing according to an assigned level of said multiple level hierarchy of a component formed by cells bounded by the perimeter.

8. A method for designing an integrated circuit (IC) comprising the steps of:

a. generating a hierarchical logic design defining said IC as a hierarchy of interconnected components and cells, wherein said hierarchy comprises multiple levels including a lowest level and at least one higher level, wherein each of said component is assigned to one of said multiple levels, wherein said hierarchical logic design defines each component assigned to said lowest level as being formed by a plurality of said cells, and wherein each component assigned to each of said higher levels is formed by at least one component assigned to lower levels of said hierarchy;

b. processing said hierarchical logic design to generate an IC layout wherein each cell of the IC is assigned to a unique position within an IC substrate, wherein said unique position for each cell forming each component is determined based on criteria other than one of placing all cells forming a same component within a particular portion of said substrate;

c. analyzing said IC layout and the hierarchical logic design to identify positions within said substrate to which cells forming each component of said hierarchy were assigned at step b; and

d. determining from the positions identified at step c, a shape and position of each of a plurality of areas of said layout, wherein each component of said multiple-level hierarchy corresponds to at least one area of said plurality of areas, and wherein each area of said plurality of areas has a perimeter sized and shaped to encompass cells which the hierarchical design defines as forming the area'"'"'s corresponding component.

9. The method of claim 8 further comprising the step of:

e. generating a first display depicting perimeters of each of said plurality of areas of said substrate determined at step d for which said hierarchical design assigned the areas'"'"' corresponding components to a particular single level of said hierarchy, perimeters of all others of said plurality of areas determined at step c being excluded from said first display.

10. The method of claim 9 wherein one of the perimeters depicted in said display corresponds to a particular one of said components which said hierarchical design defines as residing on said particular level of said hierarchy and as being formed by a plurality of components residing at a next lower level of said hierarchy, the method further comprising the steps of:

f. selecting said one of said perimeters depicted in said first display, and

g. modifying said display so that it depicts perimeters of each of said plurality of areas of said substrate corresponding to components forming said particular one of said components.