Test structure and methodology for characterizing etching in an integrated circuit fabrication process

• US 6,258,437 B1
• Filed: 03/31/1999
• Issued: 07/10/2001
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Jarvis, Richard W.
• Primary Examiner(s): WATKINS III, WILLIAM P
• Application Number:
  US09/282,329
• Time in Patent Office: 832 Days
• Field of Search: 428/131, 428/137, 428/195, 428/203, 428/201, 428/156, 257/432, 257/431, 257/435, 257/436, 438/16, 324/501, 324/751, 324/752, 324/765, 324/766, 324/767, 324/768, 324/769
• US Class Current: 428/137
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24273 including aperture
• CPC Class Codes: Y10T 428/24322 Composite web or sheet
• CPC Class Codes: Y10T 428/24479 including variation in thickness
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
• CPC Class Codes: Y10T 428/24851 Intermediate layer is discontinuous or differential
• CPC Class Codes: Y10T 428/24868 Translucent outer layer

Abstract

A test structure for characterizing etching procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a contrast layer, a simulated substrate, and a pattern layer arranged in order upon a substrate. The simulated substrate includes portions mimicking a semiconductor substrate and portions mimicking isolation regions. Etching of the pattern layer may be performed according to a procedure used in the fabrication of integrated circuits. The contrast layer may be selectively etched relative to the substrate, the simulated substrate, and the pattern layer. Exposure of the etched test structure to a wet etchant selective for the contrast layer may be used to identify defects resulting from over-etching or other errors in the integrated circuit fabrication procedure being tested.

Claims

1. A test structure for characterizing local interconnect formation, comprising:

a contrast layer residing above a substrate;

a simulated substrate including a first material residing laterally adjacent a second material, both of which reside upon the contrast layer; and

a pattern layer residing upon said simulated substrate, wherein the pattern layer includes openings extending therethrough to the lateral boundary between the first and second materials.

2. The test structure as recited in claim 1, wherein said contrast layer comprises a material having etch properties different from etch properties of said substrate, said simulated substrate, and said pattern layer.

3. The test structure as recited in claim 1, wherein said contrast layer comprises silicon nitride.

4. The test structure as recited in claim 1, wherein a thickness of said contrast layer is substantially between about 1000 angstroms and about 1400 angstroms.

5. The test structure as recited in claim 3, wherein said substrate comprises single crystalline silicon having a layer of silicon dioxide upon an upper surface thereof.

6. The test structure as recited in claim 5, wherein a thickness of said layer of silicon dioxide is substantially between about 300 angstroms and about 500 angstroms.

7. The test structure as recited in claim 1, wherein said first material comprises polycrystalline silicon, and wherein said second material comprises silicon dioxide.

8. The test structure as recited in claim 1, wherein a thickness of said simulated substrate is substantially between about 1800 angstroms and about 2200 angstroms.

9. The test structure as recited in claim 1, wherein said pattern layer comprises silicon dioxide.

10. The test structure as recited in claim 1, wherein a thickness of said pattern layer is substantially between about 6000 angstroms and about 8000 angstroms.

11. The test structure of claim 1, wherein a width of one or more of said openings is less than approximately 1 μ

m.

12. The test structure of claim 1, wherein said openings are spaced across the test structure, and wherein at least a portion of the openings span the interface between the first material and the second material.

13. The test structure of claim 1, wherein said first material comprises one or more meandering lines.

14. The test structure of claim 1, wherein said second material comprises one or more meandering lines.