Method to form a high Q inductor

• US 6,258,688 B1
• Filed: 03/15/2000
• Issued: 07/10/2001
• Est. Priority Date: 03/15/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chao-chieh
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/525,671
• Time in Patent Office: 482 Days
• Field of Search: 438/618, 438/381, 257/516, 257/531
• US Class Current: 438/381
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of a high Q inductor. STI trenches are etched for both the active region and the inductor region. The location of the STI region for the inductor is removed from the active region by a significant distance. A thick layer of photoresist is deposited over the surface of the substrate that does not coincide with the surface of the substrate over which the inductor is to be created. A high-energy ion implant is performed after which the thick layer of photoresist is removed. The inside surfaces of the STI trenches are lined after which the STI trenches are filled and the process of creating the semiconductor device proceeds, using conventional methods of fabrication of active components and the inductor whereby the inductor is created overlying the surface of the substrate into which the high-energy ion implant has been performed.

Claims

1. A method of creating a high-Q inductor on a surface of a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is divided into an active region adjacent to a region of electrical isolation adjacent to a region over which at least one inductor is to be created;

performing an N+ implant into a surface of said substrate thereby whereby said region of N+ implant is located in said region of electrical isolation and immediately adjacent to said region over which at least one inductor is to be created;

creating a trench for a first Shallow Trench Isolation in a surface of said substrate whereby said trench for a first Shallow Trench Isolation is located in said region of electrical isolation and immediately adjacent to said active region;

creating a trench for a second Shallow Trench Isolation in the surface of said substrate whereby said trench for a second Shallow Trench Isolation is adjacent to said N+ implant and underlies said surface region of said substrate over which at least one inductor is to be created;

depositing and patterning a thick layer of protective material whereby said pattern removes said protective material from above said trench for a second Shallow Trench Isolation thereby exposing said trench for a second Shallow Trench Isolation;

performing a high-energy ion implant into said exposed trench for a second Shallow Trench Isolation;

removing said thick layer of protective material; and

performing backend processing thereby creating conducting interconnects to at least one point of electrical contact to devices contained in said active regions thereby furthermore creating at least one inductor overlying said surface region of said substrate over which at least one inductor is to be created.

2. The method of claim 1 wherein said backend processing comprises the steps of:

depositing a layer electrically isolating material in said trench for a first Shallow Trench Isolation and in said trench for a second Shallow Trench Isolation and planarizing a surface of said deposited layer of electrically isolating material down to a surface of said substrate;

depositing a layer of low-K polysilicon over a surface of said substrate;

creating a first pattern of redistribution vias in said layer of low-K polysilicon whereby said first pattern aligns with at least one point of electrical contact of at least one active device in said active region of said substrate;

creating at least one inductor on a surface of said layer of low-K polysilicon;

depositing a layer of high-K polysilicon over a surface of said layer of low-K polysilicon;

creating a second pattern of redistribution vias in said layer of high-K polysilicon whereby said second pattern of redistribution vias aligns with said first pattern of redistribution vias in addition to connecting to at least one inductor; and

creating a network of conductive interconnect lines overlying said layer of high-K polysilicon whereby said network of conductive interconnect lines aligns with at least one point of electrical contact in said second pattern of redistribution vias.

3. The method of claim 1 wherein said performing an N+ implant into a surface of said substrate is implanting arson or phosphorous at an energy between about 25 and 75 KeV and a dose between about 5E11 and 5E13 atoms/cm³.

4. The method of claim 1 wherein said thick layer of protective material contains material selected from the group containing photoresist and dielectric material and insulation material and passivation material or any other suitable material that can serve as an effective block to high-energy ion implant.

5. The method of claim 1 wherein said high-energy ion implant is an implant of either amorphous silicon or germanium or tin (Sn) performed at an energy of about 1 to 20 MeV and at a dose of about 1×

10¹⁵ to 1×

10¹⁶ atoms/cm².

6. The method of claim 1 with the additional processing steps of creating a liner of pad oxide on the inside surfaces of said trench for said first Shallow Trench Isolation and said trench for said second Shallow Trench Isolation to a thickness of between about 100 and 500 Angstrom through a thermal oxidation method at a temperature of about 900 degrees C. for a time period of about 10 to 20 minutes said additional processing steps to be performed immediately prior to said performing backend processing.

7. A method of creating a high-Q inductor on a surface of a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is divided into an active region adjacent to a region of electrical isolation adjacent to a region over which at least one inductor is to be created;

performing an N+ implant into a surface of said substrate by implanting arson or phosphorous at an energy between about 25 and 75 KeV and a dose between about 5E11 and 5E13 atoms/cm³ into a surface of said substrate thereby creating a region of N+ implant whereby said region of N+ implant is located in said region of electrical isolation and immediately adjacent to said region over which at least one inductor is to be created and is furthermore immediately adjacent said latter region;

creating a trench for a first Shallow Trench Isolation in a surface of said substrate whereby said trench for a first Shallow Trench Isolation is located in said region of electrical isolation and immediately adjacent to said active region furthermore creating a trench for a second Shallow Trench Isolation in a surface of said substrate whereby said trench for a second Shallow Trench Isolation is adjacent to said N+ implant and underlies said surface region of said substrate over which at least one inductor is to be created;

depositing and patterning a thick layer of protective material whereby said pattern removes said protective material from above said trench for a second Shallow Trench Isolation thereby exposing said trench for a second Shallow Trench Isolation;

performing a high-energy ion implant into said exposed trench for a second Shallow Trench Isolation by implanting amorphous silicon or germanium or tin performed at an energy of about 1 to 10 MeV and at a dose of about 1×

10¹⁵ to 1×

10¹⁶ atoms/cm;

removing said thick layer of protective material; and

performing backend processing thereby creating conducting interconnects to at least one point of electrical contact to devices contained in said active regions thereby furthermore creating at least one inductor overlying said surface region of said substrate over which at least one inductor is to be created.

8. The method of claim 7 wherein said thick layer of protective material contains material selected from the group containing photoresist and dielectric material and insulation material and passivation material or any other suitable material that can serve as an effective block to high-energy ion implant.

9. The method of claim 7 wherein said backend processing comprises the steps of:

depositing a layer electrically isolating material in said trench for a first Shallow Trench Isolation and in said trench for a second Shallow Trench Isolation and planarizing a surface of said deposited layer of electrically isolating material down to a surface of said substrate;

depositing a layer of low-K polysilicon over a surface of said substrate;

creating a first pattern of redistribution vias in said layer of low-K polysilicon whereby said first pattern aligns with at least one point of electrical contact of at least one active device;

creating at least one inductor on a surface of said layer of low-K polysilicon;

depositing a layer of high-K polysilicon over a surface of said layer of low-K polysilicon;

creating a second pattern of redistribution vias in said layer of high-K polysilicon whereby said second pattern of redistribution vias aligns with said first pattern of redistribution vias in addition to connecting to at least one inductor; and

creating a network of conductive interconnect lines overlying said layer of high-K polysilicon whereby said network of conductive interconnect lines aligns with at least one point of electrical contact in said second pattern of redistribution vias.

10. The method of claim 7 with the addition processing steps of creating a liner of pad oxide on the inside surfaces of said trench for said first Shallow Trench Isolation and said trench for said second Shallow Trench Isolation to a thickness of between about 100 and 500 Angstrom through a thermal oxidation method at a temperature of about 900 degrees C. for a time period of about 10 to 20 minutes said additional processing steps to be performed.