Dislocation suppression by carbon incorporation

• US 6,258,695 B1
• Filed: 02/04/1999
• Issued: 07/10/2001
• Est. Priority Date: 02/04/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dunn, James, St. Onge, Stephen, Geiss, Peter
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US09/244,959
• Time in Patent Office: 887 Days
• Field of Search: 438/423, 438/424, 438/528, 438/520, 438/FOR.158, 438/FOR.227, 438/700, 438/702
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76213 introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence

Abstract

A method of reducing the formation of silicon crystal defects due to extrinsic stresses in an integrated circuit chip. The source of such extrinsic stresses may be filling trenches with polycrystalline silicon or oxide, silicides, forming silicon nitride spacers or liners, or during oxide birds-beak formation, or at numerous other processing points. At an appropriate point, as each sensitive feature is defined or formed, carbon co-implanted into the silicon wafer at or near the feature.

Claims

1. A method of relieving extrinsic stress in a patterned semiconductor comprising the steps of:

forming a pad passivation layer on a semiconductor layer;

etching a pattern in said pad passivation layer;

implanting carbon into said pad passivation layer and into said semiconductor layer at said etched passivation layer pattern; and

forming features defined by said etched pad passivation layer pattern,

wherein the semiconductor layer is a silicon wafer and the pattern is a shallow trench isolation pattern, said method comprising before the step of implanting carbon the steps of;

etching said silicon wafer through said defined shallow trench isolation pattern, trenches being formed to a predetermined depth and having said shallow trench isolation pattern; and

forming an oxide layer in said trenches,

wherein the carbon is implanted into said silicon wafer in said trenches.

2. The method of claim 1 wherein the step of forming the pad passivation layer comprises the steps of:

growing an oxide layer on said silicon wafer; and

forming a nitride layer on said oxide layer.

3. The method of claim 2 wherein the step of forming the features defined by said etched pattern comprises the steps of:

filling said trenches with oxide;

planarizing said oxide;

removing said pad nitride layer; and

removing said pad oxide layer.

4. A method of forming an integrated circuit having reduced extrinsic stress as in claim 2, said method further comprising the step of:

forming said integrated circuit, said trenches isolating individual transistors from neighboring transistors.

5. A method of relieving extrinsic stress in a patterned semiconductor comprising the steps of:

forming a pad passivation layer on a semiconductor layer;

etching a pattern in said pad passivation layer;

etching said silicon wafer at said pattern to form a trench, the trench being formed to a predetermined depth;

forming an oxide layer in said trench;

implanting carabon into said pad passivation layer and into said silicon wafer in said trench; and

forming features defined by said etched pad passivation layer pattern.

6. The method of claim 5 wherein:

the semiconductor layer is a silicon wafer and the teched pattern is a shallow trench isolation pattern; and

the steps of said etching said silicon wafer and said forming said oxide layer is performed before the step of implanting carbon.

7. The method of claim 6, further comprising:

filling said trenches with oxide;

planarizing said oxide;

removing said pad nitride layer, and

removing said pad oxide layer.