Low cost mixed memory integration with FERAM

• US 6,259,126 B1
• Filed: 11/23/1999
• Issued: 07/10/2001
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis Lu-Chen, Mandelman, Jack A., Assaderaghi, Fariborz
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/447,628
• Time in Patent Office: 595 Days
• Field of Search: 257/295, 257/298, 257/303, 257/304, 257/306, 257/315, 257/903, 257/904, 257/906, 257/908, 365/182, 365/185.01, 365/185.14, 365/51
• US Class Current: 257/298
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate.

Claims

1. A semiconductor memory device, comprising:

a FERAM cell structure;

a SRAM cell structure, and

a DRAM cell structure;

wherein said FERAM structure, said SRAM cell structure and said DRAM cell structure are on the same substrate and have gate surfaces which are substantially coplanar.

2. The semiconductor memory device as claimed in claim 1, further comprising a flash memory cells structure on said same substrate.

3. The semiconductor memory device as claimed in claim 1, wherein all of said cell structures have lower gate surfaces which are substantially coplanar.

4. The semiconductor memory device as claimed in claim 1, wherein said FERAM cell structure includes a node top surface which is substantially coplanar with a gate top surface of another of said cell structures.

5. A semiconductor memory device, comprising:

a FERAM cell structure;

a SRAM cell structure, and

a NVRAM cell structure;

wherein all of said cell structures are on the same substrate and include gate surfaces which are substantially coplanar.

6. The semiconductor device as claimed in claim 5, wherein at least two of said cell structures have lower gate surfaces which are substantially coplanar.

7. A semiconductor memory device, comprising:

a DRAM cell structure;

an NVRAM cell structure;

SRAM cell structure, and

a FERAM cell structure;

wherein all of said cell structures are on the same substrate and have sate surfaces which are substantially coplanar.