Integrated circuit container having partially rugged surface

• US 6,259,127 B1
• Filed: 04/30/1998
• Issued: 07/10/2001
• Est. Priority Date: 12/19/1995
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pan, Pai-Hung
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US09/070,327
• Time in Patent Office: 1,167 Days
• Field of Search: 257/309, 257/308, 257/301, 257/303, 257/306, 438/398, 438/255, 438/254
• US Class Current: 257/301
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

Disclosed is a bi-level container capacitor in which a bottom portion is smooth and an upper portion is rugged or rough. Once the container has been formed within a thick insulating layer, a conductive layer is conformally deposited over the container interior surfaces. The bottom portion of the container, which is narrowly confined between two gate electrodes, is isolated from further processing by filling the bottom portion with a protective film. A rugged conductive layer is then formed only on the surface of the upper portion of the container, after which the protective film is removed from the bottom portion. As a result, a capacitor bottom plate conforms to the interior surfaces of the container, the bottom plate including a rugged upper portion and a smooth bottom portion.

Claims

1. A container structure formed within an integrated circuit, the container comprising:

an insulating layer covering a semiconductor substrate and at least two gate electrodes, the insulating layer having a cavity therethrough, the cavity defined by an upper sidewall, a lower sidewall, and the substrate, the lower sidewall confined between the gate electrodes;

a lower conductive layer conformally coating the lower sidewall and the substrate between the two gate electrodes, the lower conductive layer having a smooth inner surface defining a first width;

an upper conductive layer conformally coating substantially all of the upper sidewall, the upper conductive layer having a rugged inner surface defining a second width wider than the first width; and

a capacitor dielectric layer conformally coating each of the smooth inner surface and the rugged inner surface.

2. The container structure as defined by claim 1, wherein the lower conductive layer comprises a polysilicon.

3. The container structure as defined by claim 1, wherein the upper conductive layer comprises a polysilicon layer having a plurality of hemispherical silicon grains thereupon.

4. The container structure as defined by claim 3, wherein a bottom part of the upper sidewall, adjacent the lower conductive layer, is devoid of hemispherical silicon grains.

5. A container-shaped capacitor bottom plate for an integrated circuit capacitor, formed above a semiconductor substrate of an integrated circuit, the container-shaped capacitor bottom plate having a lower narrow portion of an outer width less than about 0.35 micron and an upper portion including an upper conductive layer with a rugged inner surface having a hemispherical grain morphology and defining an upper inner width, the lower portion including a lower conductive layer with a substantially smooth inner surface defining a lower inner width which is less than the upper inner width, the smooth inner surface electrically connected to both the rugged inner surface and the substrate, each of the rugged inner surface and the smooth inner surface contributing to the capacitance of the capacitor.

6. The capacitor bottom plate of claim 5, wherein the lower conductive layer comprises a silicon layer.

7. The capacitor bottom plate of claim 6, wherein the upper conductive layer has a thickness of greater than about 800 Å

and the lower conductive layer has a thickness of less than about 700 Å

.

8. A container-shaped capacitor formed within an integrated circuit, the container comprising:

an insulating layer covering a semiconductor substrate, the insulating layer having a cavity therethrough, the cavity defined by a sidewall and the substrate, the sidewall having a first end adjacent the substrate and a second end, the first end defining a first inner width and the second end defining a larger second inner width;

a smooth conductive layer conformally coating the first end of the sidewall and the substrate;

a rugged conductive layer coating the second end of the sidewall; and

a capacitor dielectric layer directly contacting both the smooth conductive layer and the rugged conductive layer.

9. A container-shaped capacitor bottom plate for an integrated circuit capacitor, formed above a semiconductor substrate of an integrated circuit, the container-shaped capacitor bottom plate having a first portion and a second portion having an outer width less than that of the first portion, the first portion including a first conductive layer with a rugged charge storage surface, the second portion including a second conductive layer with a substantially smooth charge storage surface electrically connected to both the rugged charge storage surface and the substrate, the smooth charge storage surface defining an inner width less than that defined by the rugged charge storage surface.

10. The capacitor bottom plate of claim 9, wherein the outer width of the second portion is less than about 0.35 micron.

11. The capacitor bottom plate of claim 9, wherein the rugged charge storage surface has a hemispherical grain morphology.