Bond pad for stress releif between a substrate and an external substrate

• US 6,259,163 B1
• Filed: 10/07/1998
• Issued: 07/10/2001
• Est. Priority Date: 12/25/1997
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Egawa, Yoshimi, Ohuchi, Shinji, Anzai, Noritaka
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/167,529
• Time in Patent Office: 1,007 Days
• Field of Search: 257/737, 257/738, 257/773, 257/775, 257/778, 257/779, 257/780, 257/777, 257/781, 257/786, 438/108, 438/612, 438/613, 438/614, 438/FOR.343, 438/615, 361/764, 361/772, 361/773, 361/774, 361/777, 361/760
• US Class Current: 257/779
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0384 involving a mechanical process, e.g. planarising the bonding area
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 2201/0191 : wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/09736 : Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2201/099 : Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3452 : Solder masks
• CPC Class Codes: H05K 3/3457 : Solder materials or compositions; Methods of application thereof
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

A metal pattern 4 is formed at a rear surface of a substrate 3 at a front surface of which a molded semiconductor chip is mounted, the metal pattern 4 is covered with an insulating film 5 except at its connecting area 4a and a solder ball 6 is bonded to the connecting area 4a. The area of the metal pattern 4 other than the connecting area 4a inclines toward the substrate 3 and gradually becomes thinner toward the outside. Stress, which is applied to the solder ball 6, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks X is reduced and the solder ball which is used to achieve connection with an external substrate is effectively prevented from becoming electrically disconnected.

Claims

1. A semiconductor device comprising:

a substrate having front and rear surfaces;

a semiconductor chip placed on the front surface of said substrate; and

a conductive pattern formed on the rear surface of said substrate, said conductive pattern having a connecting area to be bonded with a solder bump, a first area outside said connecting area, and a portion of the first area being covered with an insulating film, a thickness of said insulating film and the first area continuously decreasing from the rear surface of said substrate to a contact surface of said connecting area.

2. A semiconductor device according to claim 1, wherein a thickness of said conductive pattern in the first area gradually decreases with increasing distance from the connecting area.

3. A semiconductor device according to claim 2, wherein a portion of said rear surface of said substrate that corresponds to the connecting area distends toward the solder bump, with the first region formed in a shape conforming to the shape of the distension.

4. A semiconductor device according to claim 1, wherein:

said solder bump is formed in a roughly spherical shape.

5. A semiconductor device according to claim 1, wherein:

said semiconductor chip is at least partially molded.

6. A semiconductor device comprising:

a substrate having front and rear surfaces;

a semiconductor chip placed on the front surface of said substrate; and

a conductive pattern formed on the rear surface of said substrate, said conductive pattern having a connecting area to be bonded with a solder bump, a first area outside the connecting area, and a staged portion between the connecting area and the first area, the first area and a portion of the staged portion being covered with an insulating film, a thickness of said insulating film continuously decreasing from a start of the staged portion to a contact surface of said connecting area.

7. A semiconductor device according to claim 6, wherein:

said solder bump is formed in a roughly spherical shape.

8. A semiconductor device according to claim 6, wherein:

said semiconductor chip is at least partially molded.

9. A semiconductor device according to claim 6, wherein said connecting area has a projecting portion projecting further out toward said solder bump relative to said insulating film, said projecting portion to extend into the solder bump.