Delay circuitry, clock generating circuitry, and phase synchronization circuitry
First Claim
1. Delay circuitry comprising:
- phase locked loop means for comprising a phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to a phase difference between the phases of the reference clock and the another clock, for generating the another clock using at least a plurality of first delay elements connected into a loop, a time delay provided by each of the plurality of first delay elements being controlled by the control signal, and for changing the value of the control signal so that the another clock is made to be in phase with the reference clock;
storage means for storing information to set a predetermined time delay; and
delay means, connected to said storage means, and including a plurality of second delay elements each of which provides an input with a time delay that is controlled by the control signal from said phase locked loop means, for determining the number of second delay elements through which an input signal is to be passed according to the information stored in said storage means, so as to provide the input signal with the predetermined time delay.
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Abstract
Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock. The delay circuitry further includes a register for storing information to set a certain time delay, and a delay unit including a plurality of delay elements each of which provides an input with a time delay that is controlled by the control signal from the PLL, for determining the number of delay elements through which an input signal is to be passed according to the information stored in the register, so as to provide the input signal with the predetermined time delay.
155 Citations
20 Claims
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1. Delay circuitry comprising:
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phase locked loop means for comprising a phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to a phase difference between the phases of the reference clock and the another clock, for generating the another clock using at least a plurality of first delay elements connected into a loop, a time delay provided by each of the plurality of first delay elements being controlled by the control signal, and for changing the value of the control signal so that the another clock is made to be in phase with the reference clock;
storage means for storing information to set a predetermined time delay; and
delay means, connected to said storage means, and including a plurality of second delay elements each of which provides an input with a time delay that is controlled by the control signal from said phase locked loop means, for determining the number of second delay elements through which an input signal is to be passed according to the information stored in said storage means, so as to provide the input signal with the predetermined time delay. - View Dependent Claims (2, 3, 4)
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5. Clock generating circuitry comprising:
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at least a delay circuit including phase locked loop means for comprising a phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to a phase difference between the phases of the reference clock and the another clock, for generating the another clock using at least a plurality of firs delay elements connected into a loop, a time delay provided by each of the plurality of first delay elements being controlled by the control signal, and for changing the value of the control signal so that the another clock is made to be in phase with the reference clock, storage means for storing information to set a predetermined time delay, and delay means connected to said storage means and including a plurality of second delay elements each of which provides an input with a time delay that is controlled by the control signal from said phase locked loop means, for determining the number of second delay elements through which an input signal is to be passed according to the information stored in said storage means, so as to provide the input signal with the predetermined time delay; and
clock generating means that forms a loop together with at least said delay circuit, for generating and furnishing a clock pulse having a certain basic pulse repetition period to said delay circuit, and for generating a clock having a predetermined pulse repetition period in cooperation with said delay circuit. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. Phase synchronization circuitry comprising:
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phase locked loop means for comprising a phase of a first reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to a phase difference between the phases of the first reference clock and the another clock, for generating the another clock using at least a plurality of first delay elements connected into a loop, a time delay provide by each of the plurality of first delay elements being controlled by the control signal, and for changing the value of the control signal so that the another clock is made to be in phase with the first reference clock;
storage means for storing information to set a predetermined time delay;
delay means including a plurality of second delay elements each of which provides an input with a time delay that is controlled by the control signal from said phase locked loop means, for changing the number of second delay elements through which an input clock signal is to be passed, so as to provide the input clock signal with the predetermined time delay; and
phase synchronization means, connected to said storage means, for comparing the phase of a second reference clock applied to thereto with that of an output clock signal from said delay means, and for changing the information stored in said storage means so that the second reference clock is made to be in phase with the output clock signal. - View Dependent Claims (20)
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Specification