Read and write operations using constant row line voltage and variable column line load

• US 6,259,627 B1
• Filed: 01/27/2000
• Issued: 07/10/2001
• Est. Priority Date: 01/27/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Multi Level Memory Technology
• Inventors: Wong, Sau Ching
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/493,026
• Time in Patent Office: 530 Days
• Field of Search: 365/185.21, 365/185.22, 365/185.03, 365/185.19
• US Class Current: 365/185.21
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A read operation for a multi-level or a multi-bit-per-cell non-volatile memory biases a selected row line cell at a fixed voltage that is above the maximum possible threshold voltage representing data and changes the column line load for a selected column line. The column line load that corresponds to the trip-point of a sense amplifier indicates the data stored in the memory cell coupled to the selected row and column lines. A corresponding write process uses the same fixed row line voltage for both program and verify cycles. The programming voltage can be the same as the row line voltage for the read operation or can depend on the data value being written. To better control programming, the duration of the program cycles and/or the load on the drain or source of the selected memory cell during a program cycle varies with time and depends on the value being written. One memory in accordance with the invention includes variable column line loads for use during read and write operations. The variable loads can select the programming current for the write operation or the bias for the read operation according to a data value and/or a count. A counter generating the count for the variable loads can be used during a read operation to change the column line bias until the trip-point of a sense amplifier is found and during a write operation to reduce programming current when the threshold voltage of the selected memory cell nears the target threshold voltage level.

Claims

1. A read operation for a memory, comprising:

biasing a selected row line at a first voltage, wherein the selected row line is coupled to a control gate of a selected memory cell, and the first voltage is higher than any threshold voltage used to represent data in the memory;

connecting a sense amplifier to a selected column line that is coupled to the selected memory cell;

applying a selected load to the selected column line;

determining a state of the sense amplifier while the selected row line is at the first voltage and the selected load is applied to the selected column;

in response to the sense amplifier having a first state, changing the selected load and repeating the applying and determining steps; and

in response to the sense amplifier having a second state, generating a read value for the selected memory cell according to the selected bias.

2. The read operation of claim 1, wherein:

the first state arises when current through the selected memory cells trips the sense amplifier; and

the second state arises when the current through the selected memory cells fails to trip the sense amplifier.

3. The read operation of claim 1, wherein:

the first state arises when current through the selected memory cells fails to trip the sense amplifier; and

the second state arises when the current through the selected memory cells trips the sense amplifier.

4. The read operation of claim 1, further comprising keeping the selected row line at the first voltage throughout the read operation.

5. The read operation of claim 1, wherein changing the selected load comprises repeating the determining and changing steps as required to perform a binary search for a load corresponding to a trip point of the sense amplifier.

6. The read operation of claim 1, wherein the first voltage is equal to a voltage applied to the selected row line when writing a data value.

7. The read operation of claim 6, wherein the data value corresponds to a threshold voltage that is lowest of any threshold voltage representing stored data values.

8. A read operation for a memory, comprising:

biasing a selected row line at a first voltage, wherein the selected row line is coupled to a control gate of a selected memory cell, and the first voltage is higher than any threshold voltage used to represent data in the memory;

connecting a sense amplifier to a selected column line that is coupled to the selected memory cell;

applying a selected load to the selected column line;

determining a state of the sense amplifier while the selected row line is at the first voltage and the selected load is applied to the selected column;

in response to the sense amplifier having a first state, changing the selected load and repeating the applying and determining steps, wherein changing the selected load comprises operating a counter that provides a count signal as a control signal for a variable load; and

in response to the sense amplifier having a second state, generating a read value according to the selected bias.

9. The read operation of claim 8, further comprising repeating the determining and changing steps m times, wherein m is the number of bits in the control signal.

10. The read operation of claim 9, wherein operating the counter comprises:

selecting a steps size for the counter according to the number of previous repetitions of the changing step; and

selecting whether to count up or down according to the result of a preceding repetition of the determining step.

11. A memory comprising:

a memory array including rows and columns of memory cells, wherein each row of the array has a row line coupled to memory cells in the row, and each column has a column line coupled to memory cells in the column;

a column decoder coupled to the column lines of the memory array;

a first variable load between the column decoder and a source of a first voltage; and

a counter coupled to the first variable load, wherein a count signal from the counter controls the first variable load.

12. The memory of claim 11, further comprising a converter coupled to the counter, wherein for a read operation, the converter converts the count signal to a multibit data value for output as a value read from a selected memory cell.

13. The memory of claim 11, further comprising:

a second variable load between the column decoder and a source of a second voltage; and

a control circuit that applies the second voltage through the second variable load to the column decoder during a write operation, and applies the first voltage through the first variable load to the column decoder during a read operation.

14. The memory of claim 13, wherein the control circuit applies the second voltage through the second variable load to the column decoder during program cycles of the write operation and applies the first voltage through the first variable load to the column decoder during verify cycles of the write operation.

15. The memory of claim 11, further comprising:

a source of a second voltage that is greater than any threshold voltage used to represent data stored in the memory; and

a row decoder coupled to the source of the second voltage and to the row lines of the memory array, wherein the row decoder applies the second voltage to a selected row line throughout a read operation.

16. The memory of claim 15, wherein the row decoder applies the second voltage to a selected row line throughout a write operation.

17. The memory of claim 15, further comprising a voltage shifter that provides a programming signal having a voltage level that depend on a data value being written during a write operation, wherein the row decoder applies the programming signal to a selected row line throughout the write operation.

18. The memory of claim 15, further comprising:

a sense amplifier, wherein the column decoder connects the first variable load and the sense amplifier to a selected column line for a read operation; and

a read circuitry that operates the counter to change the first variable load during the read operation and that generates a read value from a count selected from the counter according a state of the sense amplifier.

19. The memory of claim 18, further comprising a converter coupled to the counter, wherein for the read operation, the converter converts the count signal to a multibit data value for output as a value read from a selected memory cell.

20. The memory of claim 19, wherein the converter further comprises a volatile memory for storing counts from the counter, wherein each count corresponds to a reference cell and is a value of the count signal at a trip point of the sense amplifier when the sense amplifier is coupled to the reference cell.

21. A write operation for a non-volatile multi-level memory, comprising:

(a) applying a programming pulse to a selected memory cell to change a threshold voltage of the selected memory cell;

(b) sensing a state of a sense amplifier connected to the selected memory cell when the selected memory cell is biased for sensing;

(c) repeating the applying and sensing steps until the sensing first determines the sense amplifier has a first state;

(d) sensing the state of the sense amplifier again to confirm the first determination whether the sense amplifier had the first state;

(e) in response to failing to confirm, applying a further programming pulse to the selected memory cell to change the threshold voltage of the selected memory cell; and

(f) in response to confirming the first determination, ending the write operation.

22. The method of claim 21, further comprising repeating steps (d) and (e) until step (d) confirms the sense amplifier has the first state.

23. The method of claim 21, wherein the programming pulse of step (e) has parameters that minimize change in the threshold voltage of the selected memory cell caused by the programming pulse of step (e).

24. The method of claim 23, wherein the programming pulse of step (e) has a minimum pulse-width.

25. The method of claim 23, wherein the programming pulse of step (e) has a minimum programming current.

26. A write operation for a multi-bit-per-cell non-volatile memory, comprising:

biasing a selected row line at a first voltage, wherein the selected row line is coupled to a control gate of a selected memory cell;

performing a programming operation by connecting a first load to a selected column line, wherein the selected column line is coupled to the selected memory cell and the first load provides a programming current that changes a threshold voltage of the selected memory cell during the programming operation;

selecting a second load that corresponds to a multi-bit value that the write operation writes in the selected memory cell;

performing a verify operation that comprises;

connecting the second load and a sense amplifier to the selected column line, wherein the selected row line remains at the first voltage during the verify operation; and

determining a state of the sense amplifier while the selected row line is at the first voltage and the second load is connected to the selected column;

in response to the sense amplifier having a first state during the verify operation, repeating the programming operation and the verify operation; and

ending the write operation in response to the sense amplifier having a second state during the verify operation.

27. A multi-bit-per-cell memory comprising:

a memory array including rows and columns of memory cells, wherein each row of the array has a row line coupled to memory cells in the row, and each column has a column line coupled to memory cells in the column;

a column decoder coupled to the column lines of the memory array;

a first variable load coupled to the column decoder;

a sense amplifier coupled to the column decoder; and

a control circuit connected to the first variable load, wherein for a write operation, the control circuit receives a multibit value to be written in a selected memory cell and controls the first variable load to bias a selected column line for a verify cycle of the write operation, the control circuit controlling the first variable load so that a trip point of the sense amplifier during the verify cycle depends on the multibit value.

28. The memory of claim 27, further comprising a second load coupled to the column decoder, wherein the second load provides a programming current to change a threshold voltage of the selected memory cell during a program cycle.