Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories
First Claim
1. Circuit for the regulation of the row voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more rows of the memory when said one or more rows are being selected, the voltage regulator comprising charge boosting means coupled to an output of said voltage regulator and configured to be activated upon the selection of said one or more memory rows in order to boost said regulated voltage upon the selection of said one or more memory rows, said charge boosting means comprise at least one condenser having a first plate coupled to the output of said voltage regulator and a second plate coupled to a voltage signal that is variable between a first potential and a second potential greater than said first potential, said voltage signal passing from said first potential to said second potential upon the selection of said one or more memory rows.
10 Assignments
0 Petitions
Accused Products
Abstract
A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.
139 Citations
19 Claims
- 1. Circuit for the regulation of the row voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more rows of the memory when said one or more rows are being selected, the voltage regulator comprising charge boosting means coupled to an output of said voltage regulator and configured to be activated upon the selection of said one or more memory rows in order to boost said regulated voltage upon the selection of said one or more memory rows, said charge boosting means comprise at least one condenser having a first plate coupled to the output of said voltage regulator and a second plate coupled to a voltage signal that is variable between a first potential and a second potential greater than said first potential, said voltage signal passing from said first potential to said second potential upon the selection of said one or more memory rows.
-
8. A circuit for providing row reading voltage in a non-volatile memory, comprising:
-
a voltage regulator circuit having an input coupled to a voltage supply and an output coupled to one or more rows of the memory; and
a boosting circuit having an input coupled to a control signal source and an output coupled to the output of the voltage regulator circuit, the boosting circuit configured to be activated in response to a control signal to supply voltage to the one or more rows of the memory, the output of the boosting circuit further connected to a variable voltage potential, the boosting circuit comprising a capacitive element coupled between the boosting circuit and the voltage regulator circuit, the capacitive element having a first terminal coupled to the boosting circuit output and a second terminal coupled to the voltage regulator output. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A circuit for providing row reading voltage in a non-volatile memory, comprising:
-
a voltage regulator circuit having an input coupled to a voltage supply and an output coupled to one or more rows of the memory;
a capacitive element having a first terminal coupled to the output of the voltage regulator circuit and a second terminal coupled to a voltage potential;
an inverter having an input coupled to a control signal source and an output coupled to the second terminal of the capacitive element; and
the voltage potential is configured to vary from a first voltage level to a second voltage level that is higher than the first voltage level in response to selection of the one or more rows of the memory. - View Dependent Claims (16, 17, 18, 19)
-
Specification