Method and apparatus for built-in self-repair of memory storage arrays

• US 6,259,637 B1
• Filed: 12/01/2000
• Issued: 07/10/2001
• Est. Priority Date: 12/01/2000
• Status: Expired due to Term

• Current Assignee: Vantage Micro LLC (Fullbrite Capital Partners, LLC)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wood, Timothy J., Tupuri, Raghuram S., Zuraski, Jr., Gerald D.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/728,285
• Time in Patent Office: 221 Days
• Field of Search: 365/200, 365/201
• US Class Current: 365/200
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

An integrated circuit device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. First and second redundant rows of memory cells and a first redundant column of memory cells are provided. A test circuit is coupled to the memory array and is adapted to test a plurality of memory cells coupled to each of the plurality of rows. A control circuit is coupled to the test circuit and is adapted to receive test results from the test circuit, the control circuit being adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit, and a third register is coupled to the control circuit and adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.

Claims

1. An integrated circuit device, comprising:

a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row and each column having coupled to it a plurality of memory cells;

a first redundant row of memory cells;

a first redundant column of memory cells;

a test circuit coupled to the memory array and adapted to test the plurality of memory cells coupled to each of the plurality of rows;

a control circuit coupled to the test circuit and adapted to receive test results from the test circuit, the control circuit adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first redundant row and first redundant column;

a first register coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit; and

a second register coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit.

2. The integrated circuit device of claim 1, further comprising:

a second redundant row of memory cells; and

,

a third register coupled to the control circuit,

the control circuit adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and the first redundant column, and the third register adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.

3. The integrated circuit device of claim 1, further comprising a first comparator coupled to the first register and coupled to receive a row address from the test unit, the first comparator adapted to compare the row address to an assignment in the first register and provide a signal to the control circuit.

4. The integrated circuit device of claim 2, further comprising a first comparator coupled to the first register and coupled to receive a row address from the test unit, the first comparator adapted to compare the row address to an assignment in the first register and provide a signal to the control circuit.

5. The integrated circuit device of claim 3, further comprising a second comparator coupled to the first register and coupled to receive a column address from the test unit, the second comparator adapted to compare the column address to an assignment in the first register and provide an output signal.

6. The integrated circuit device of claim 5, further comprising a first logic circuit having first and second input terminals and an output terminal, the first input terminal coupled to the first register, the second input terminal coupled to receive the output signal from the second comparator, and the output terminal coupled to the control circuit.

7. The integrated circuit device of claim 4, further comprising a second comparator coupled to the first register and coupled to receive a column address from the test unit, the second comparator adapted to compare the column address to an assignment in the first register and provide an output signal.

8. The integrated circuit device of claim 7, further comprising a first logic circuit having first and second input terminals and an output terminal, the first input terminal coupled to the first register, the second input terminal coupled to receive the output signal from the second comparator, and the output terminal coupled to the control circuit.

9. The integrated circuit device of claim 8, further comprising a third comparator coupled to the third register and coupled to receive a row address from the test unit, the third comparator adapted to compare the row address to an assignment in the third register and provide a signal to the control circuit.

10. The integrated circuit device of claim 9, further comprising a fourth comparator coupled to the third register and coupled to receive a column address from the test unit, the fourth comparator adapted to compare the column address to an assignment in the third register and provide an output signal.

11. The integrated circuit device of claim 10, further comprising a second logic circuit having first and second input terminals and an output terminal, the first input terminal coupled to the third register, the second input terminal coupled to receive the output signal from the fourth comparator, and the output terminal coupled to the control circuit.

12. The integrated circuit device of claim 11, further comprising a fifth comparator coupled to the second register and coupled to receive a column address from the test unit, the fifth comparator adapted to compare the column address to an assignment in the second register and provide a signal to the control circuit.

13. A method for replacing defective memory cells in a memory array, comprising:

testing a first row of memory cells in the memory array;

detecting a first defective memory cell coupled to the first row;

providing, to a control circuit, row information and column information associated with the first defective memory cell;

determining an assignment of one of a redundant row and redundant column to replace the first row;

storing the assignment in a register.

14. The method of claim 13, wherein storing the assignment in a register comprises storing the row information and the column information in a first redundant row register.

15. The method of claim 13, wherein detecting a first defective memory cell coupled to the first row further comprises detecting first and second defective memory cells coupled to the first row;

and

wherein providing, to a control circuit, row information and column information associated with the first defective memory cell further comprises providing, to a control circuit, row information and column information associated with the first defective memory cell and providing, to the control circuit, row information and column information associated with the second defective memory cell.

16. The method of claim 15, wherein storing the assignment in a register comprises storing, in a first redundant row register, the row information associated with the first and second defective memory cells.

17. The method of claim 16, further comprising:

testing a second row of memory cells in the memory array;

detecting a first defective memory cell coupled to the second row; and

providing, to the control circuit, row information and column information associated with the first defective memory cell coupled to the second row.

18. The method of claim 17, further comprising storing the row information and column information associated with the first defective memory cell coupled to the second row in a second redundant row register.

19. The method of claim 17, further comprising:

storing, in a second redundant row register, the row information stored in the first redundant row register; and

storing, in the first redundant row register, the row information and column information associated with the first defective memory cell coupled to the second row.

20. The method of claim 18, further comprising:

testing a third row of memory cells in the memory array;

detecting a first defective memory cell coupled to the third row;

providing row information and column information associated with the first defective memory cell coupled to the third row to the control circuit; and

comparing the column information associated with the first defective memory cell coupled to the third row with the column information stored in the second redundant row register.

21. The method of claim 20, further comprising:

in response to a match between the column information associated with the first defective memory cell coupled to the third row and the column information stored in the second redundant row register, storing, in a redundant column register, the column information associated with the first defective memory cell coupled to the third row, and releasing the second redundant row register to receive additional row information.

22. The method of claim 20, further comprising:

in response to a mismatch between the column information associated with the first defective memory cell coupled to the third row and the column information stored in the second redundant row register, storing the column information associated with the first defective memory cell coupled to the third row in a redundant column register.

23. The method of claim 21, further comprising:

testing a fourth row of memory cells in the memory array;

detecting a first defective memory cell coupled to the fourth row;

providing row information and column information associated with the first defective memory cell coupled to the fourth row to the control circuit;

comparing the column information associated with the first defective memory cell coupled to the fourth row with the column information stored in the redundant column register; and

in response to a mismatch between the column information associated with the first defective memory cell coupled to the fourth row and the column information stored in the redundant column register, and storing the row information and column information associated with the first defective memory cell coupled to the fourth row in the second redundant row register.

24. The method of claim 17, wherein detecting a first defective memory cell coupled to the second row further comprises detecting first and second defective memory cells coupled to the second row;

and

wherein providing, to the control circuit, row information and column information associated with the first defective memory cell coupled to the second row further comprises providing, to the control circuit, row information and column information associated with the first defective memory cell coupled to the second row and providing, to the control circuit, row information and column information associated with the second defective memory cell coupled to the second row.

25. The method of claim 24, further comprising storing, in a second redundant row register, the row information associated with the first defective memory cell coupled to the second row.

26. The method of claim 14, further comprising:

testing a second row of memory cells in the memory array;

detecting a first defective memory cell coupled to the second row;

providing, to the control circuit, row information and column information associated with the first defective memory cell coupled to the second row; and

comparing the column information associated with the first defective memory cell coupled to the second row with the column information stored in the first redundant row register.

27. The method of claim 26, further comprising:

in response to a match between the column information associated with the first defective memory cell coupled to the second row and the column information stored in the first redundant row register, storing, in a redundant column register, the column information associated with the first defective memory cell coupled to the second row, and releasing the first redundant row register to receive additional row information.

28. The method of claim 26, further comprising:

in response to a mismatch between the column information associated with the first defective memory cell coupled to the second row and the column information stored in the first redundant row register, storing, in a second redundant row register, the row information and the column information associated with the first defective memory cell coupled to the second row.

29. The method of claim 26, further comprising:

in response to a mismatch between the column information associated with the first defective memory cell coupled to the second row and the column information stored in the first redundant row register, storing, in a second redundant row register, the row information and the column information stored in the first redundant row register, and storing, in the first redundant row register, the row information and the column information associated with the first defective memory cell coupled to the second row.

30. The method of claim 26, wherein detecting a first defective memory cell coupled to the second row further comprises detecting first and second defective memory cells coupled to the second row, the method further comprising:

storing, in a second redundant row register, the row information and the column information stored in the first redundant row register; and

storing, in the first redundant row register, the row information associated with the first defective memory cell coupled to the second row.

31. The method of claim 27, further comprising:

testing a third row of memory cells in the memory array;

detecting a first defective memory cell coupled to the third row;

providing, to the control circuit, row information and column information associated with the first defective memory cell coupled to the third row; and

storing, in the first redundant row register, the row information and the column information associated with the first defective memory cell coupled to the third row.

32. The method of claim 31, further comprising:

testing a fourth row of memory cells in the memory array;

detecting a first defective memory cell coupled to the fourth row;

providing row information and column information associated with the first defective memory cell coupled to the fourth row to the control circuit;

comparing the column information associated with the first defective memory cell coupled to the fourth row with the column information stored in the redundant column register; and

in response to a mismatch between the column information associated with the first defective memory cell coupled to the fourth row and the column information stored in the redundant column register, and storing the row information and column information associated with the first defective memory cell coupled to the fourth row in the second redundant row register.