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Method and apparatus for built-in self-repair of memory storage arrays

  • US 6,259,637 B1
  • Filed: 12/01/2000
  • Issued: 07/10/2001
  • Est. Priority Date: 12/01/2000
  • Status: Expired due to Term
First Claim
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1. An integrated circuit device, comprising:

  • a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row and each column having coupled to it a plurality of memory cells;

    a first redundant row of memory cells;

    a first redundant column of memory cells;

    a test circuit coupled to the memory array and adapted to test the plurality of memory cells coupled to each of the plurality of rows;

    a control circuit coupled to the test circuit and adapted to receive test results from the test circuit, the control circuit adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first redundant row and first redundant column;

    a first register coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit; and

    a second register coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit.

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