Circuits and methods for implementing audio Codecs and systems using the same

• US 6,259,957 B1
• Filed: 04/04/1997
• Issued: 07/10/2001
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Alexander, Mark, Cope, Bryan, Prihadi, Kartika, Chowdhury, Golam, Subramonium, Krishnan
• Primary Examiner(s): Mei, Xu
• Application Number:
  US08/833,185
• Time in Patent Office: 1,558 Days
• Field of Search: 700/94, 381/119, 381/104, 381/106, 381/107, 381/22, 381/23, 341/110, 369/4, 369/5
• US Class Current: 700/94
• CPC Class Codes: G10L 19/18 Vocoders using multiple modes

Abstract

Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

Claims

1. An audio codec having multiple selectable processing paths comprising:

a first processing path comprising;

an analog input mixer for mixing analog data streams received at a plurality of analog inputs into an mixed analog data stream;

an analog to digital converter for converting said mixed analog data stream into a digital data stream;

a digital mixer for mixing data from a digital input with said digital data stream to produce a mixed digital data stream;

a digital to analog converter for converting said mixed digital data stream into a second analog stream;

an analog output mixer for mixing said second analog stream with analog data received from a second analog input, to produce an analog output stream; and

at least one output for transmitting said analog output stream to an external device; and

a second processing path comprising;

an multiplexer for selecting a data stream from among said analog data streams received at said plurality of analog inputs and said analog output stream;

an analog to digital converter for converting said data stream selected by said multiplexer into digital form; and

an output port for transmitting said selected data stream in digital form to an external device.

2. The codec of claim 1 and further comprising a third processing path comprising:

an analog to digital converter in parallel with said multiplexer for converting an analog data stream from a selected one of said plurality of analog inputs into digital form; and

an output for transmitting said stream in digital form to an external device.

3. The codec of claim 1 wherein said first processing path further comprises 3D processing circuitry for processing digital data output from said digital mixer.

4. The codec of claim 3 and further comprising a second digital mixer for optionally mixing said digital data stream output from said digital mixer with digital data from said digital input subsequent to 3D processing of said digital data output from said 3D processing circuitry.

5. The codec of claim 1 wherein said second processing path includes a digital mixer for mixing data output from said analog to digital converter of said second path with digital data received from a tap in said first processing path.

6. The codec of claim 1 wherein said output port of said first path includes volume and mute controls and an output buffer.

7. The codec of claim 6 wherein said volume and mute controls and output buffer comprise:

a first stage comprising;

an operational amplifier;

a tapped resistor having an input for receiving analog data from said analog output mixer, an output coupled to an output of said operational amplifier, and a plurality of taps for providing a sequence of voltages to a noninverting input of said operational amplifier, said each voltage of said sequence of voltages corresponding to an attentuation step by said first stage in a range from an intermediate value to a predetermined ending value; and

a second stage comprising;

an operational amplifier;

a tapped resistor having an input for receiving data from said first attenuater mixer, an output coupled to an output of said operational amplifier, an a plurality of taps for providing a sequence of voltages to a noninverting input of said operational amplifier, said each of said sequence of voltages corresponding to an attentuation step by said second stage in a range from a predetermined starting value to said intermediate value.