Apparatus and method for high performance implementation of system calls

• US 6,260,057 B1
• Filed: 03/01/1995
• Issued: 07/10/2001
• Est. Priority Date: 03/01/1995
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kleiman, Steven R., Eykholt, Joseph R.
• Primary Examiner(s): Banakhah, Majid A.
• Assistant Examiner(s): LAO, SUE X
• Application Number:
  US08/396,600
• Time in Patent Office: 2,323 Days
• Field of Search: 395/650, 395/700, 395/600, 395/672, 395/670, 395/677, 714/25, 714/38, 714/46, 709/300, 709/102, 709/100, 709/107, 709/310, 717/4
• US Class Current: 718/102
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs
• CPC Class Codes: G06F 9/4484 Executing subprograms

Abstract

A method and apparatus for bypassing multiple pre-tests and post-tests during a system call when those tests are known to be inapplicable. One or more slow path flags are checked during a system call or TRAP. If the slow path flag is clear, execution follows a fast instruction path, resulting in faster execution for the system call or TRAP. Otherwise execution follows a slow instruction path. The slow path flags are set, cleared, and checked at appropriate times. The invention improves the execution time of a thread in a software process and may be used in a data processing system employing multiple threads. Each thread in the data processing system has its own set of slow path flags. The invention can set, clear and check the slow path flags of each thread independently, in subsets of threads, or in all threads.

Claims

1. A method for improving an execution time of a system call issued by a software thread in a data processing system, comprising:

initiating the system call of the software thread; and

performing the system call, including

checking whether a slow path flag for the thread is set,

performing, when the slow path flag is set, instructions placed in a slow instruction path, and

performing, when the slow path flag is clear, instructions placed in a fast instruction path to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

2. The method of claim 1, wherein the slow instruction path includes a test condition that is not contained in the fast instruction path, and further comprising setting the slow path flag under circumstances affecting the test condition, before the checking of the slow path flag.

3. The method of claim 1, further comprising clearing the slow path flag after the checking of the slow path flag.

4. The method of claim 3, wherein the slow instruction path includes a test condition that is not contained in the fast instruction path, and performing of the slow instruction path includes determining whether the test condition is true and setting the slow path flag when the test condition is true.

5. The method of claim 1, wherein the performing of the system call includes executing instructions of a system call function, and the checking of the slow path flag is performed before the executing of the instructions of the system call function.

6. The method of claim 1, wherein the performing of the system call includes executing instructions of a system call function, and the checking of the slow path flag is performed after the executing of the instructions of the system call function.

7. The method of claim 1, wherein the slow path flag is a t_pre_test flag, indicating whether a test condition should be checked before a system call function is executed.

8. The method of claim 1, wherein the slow path flag is a t_post_test flag, indicating whether a test condition should be checked after a system call function is executed.

9. The method of claim 1, wherein the slow path flag includes a combination of an asynchronous-event flag and a signal-check flag, the combination indicating whether a test condition should be checked after a system call function is executed.

10. The method of claim 1, wherein the instructions in the slow instruction path include a plurality of test conditions to be checked before a system call function is executed.

11. The method of claim 1, wherein the instructions in the slow instruction path include a plurality of test conditions to be checked after a system call function is executed.

20. The method of claim 1 or claim 12, wherein the software thread is one of a plurality of software threads executing in a multi-threaded computer system.

12. A method for improving an execution time of a TRAP that is caused by a system event in a data processing system, comprising:

recognizing that an event causing a TRAP condition has occurred, wherein the event interrupts execution of a software thread by the data processing system; and

processing the TRAP condition, including

checking whether a slow path flag for the thread is set,

performing when the slow path flag is set, instructions placed in a slow instruction path, and

performing, when the slow path flag is clear, instructions placed in a fast instruction path to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

13. The method of claim 12, wherein the slow instruction path includes a test condition that is not contained in the fast instruction path, and further comprising setting the slow path flag under circumstances affecting the test condition before the checking of the slow path flag.

14. The method of claim 12, further comprising clearing the slow path flag, after the checking of the slow path flag.

15. The method of claim 14, wherein the slow instruction path includes a test condition that is not contained in the fast instruction path, and the performing of the slow instruction path includes determining whether the test condition is true and setting the slow path flag when the test condition is true.

16. The method of claim 12, wherein the processing of the TRAP condition includes executing instructions of a TRAP function, and the checking of the slow path flag is performed before the executing of the instructions of the TRAP function.

17. The method of claim 12, wherein the processing of the TRAP condition includes executing instructions of a TRAP function, and the checking of the slow path flag is performed after the executing of the instructions of the TRAP function.

18. The method of claim 12, wherein the slow path flag is a combination of an asynchronous-events flag indicating whether the event causing the TRAP was caused by an asynchronous event, and a signal-check flag indicating whether the asynchronous event was a signal.

19. The method of claim 18, wherein the performing of the slow instruction path includes:

performing a function to process a pending signal;

determining whether there are more pending signals in the data processing system corresponding to the thread; and

setting the signal-check flag if there are more pending signals.

21. A method for improving an execution time of a system call issued by a software process in a data processing system, comprising:

initiating the system call; and

performing the system call, including

checking whether a slow path flag for the software process is set,

performing, when the slow path flag is set, instructions placed in a slow instruction path, and

performing, when the slow path flag is clear, instructions placed in a fast instruction path to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

22. An apparatus for improving an execution time of a system call issued by a software thread in a data processing system, comprising:

circuitry performing one or more software thread instructions forming a part of the software thread, where the software thread instructions include the system call;

circuitry checking whether a slow path flag corresponding to the software thread is set;

circuitry performing, when the slow path flag is set, instructions placed in a slow instruction path of the system call; and

circuitry performing, when the slow path flag is clear, instructions placed in a fast instruction path of the system call to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

23. An apparatus for improving the execution time of a TRAP that is caused by a system event in a data processing system, comprising:

a memory storing a slow path flag for a software thread;

circuitry recognizing that an event causing a TRAP condition has occurred, wherein the event causes execution of the software thread to become interrupted;

circuitry checking whether a slow path flag corresponding to the thread is set;

circuitry performing, when the slow path flag is set, instructions placed in a slow instruction path of the TRAP; and

circuitry performing, when the slow path flag is clear, instructions in placed a fast instruction path of the TRAP to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

24. An apparatus for improving an execution time of a system call issued by a software process, comprising:

a memory storing a slow path flag for the software process;

circuitry performing software process instructions of the software process, the software process instructions including the system call;

circuitry checking whether a slow path flag for the process is set;

circuitry performing, when the slow path flag is set, instructions placed in a slow instruction path of the system call; and

circuitry performing, when the slow path flag is clear, instructions placed in a fast instruction path of the system call to avoid at least one of a pre-test or a post-test in connection with the system call when the at least one pre-test or post-test is known to be inapplicable.

25. A computer system executing a plurality of software threads, comprising:

a memory storing a first slow path flag corresponding to a first thread and a second slow path flag corresponding to a second thread;

circuitry performing first thread instructions of the first software thread, the first thread instructions including a first system call;

circuitry performing second thread instructions of the second software thread, the second thread instructions including a second system call;

circuitry checking whether a slow path flag corresponding to the first thread is set;

circuitry checking whether a slow path flag corresponding to the second thread is set;

circuitry performing, when the first slow path flag is set, instructions placed in a slow instruction path corresponding to the first system call;

circuitry performing, when the first slow path flag is clear, instructions placed in a fast instruction path corresponding to the first system call to avoid at least one of a pre-test or a post-test in connection with the first system call when the at least one pre-test or post-test is known to be inapplicable;

circuitry performing, when the second slow path flag is set, instructions placed in a slow instruction path corresponding to the second system call; and

circuitry performing, when the first slow path flag is clear, instructions placed in a fast instruction path corresponding to the second system call to avoid at least one of a pre-test or a post-test in connection with the second system call when the at least one pre-test or post-test is known to be inapplicable.

26. A method, in a processing system employing threads and at least one of system calls and TRAPs that is capable of being initiated in conjunction with execution of a plurality of the threads, comprising:

determining at least one of a pre-test and a post-test that, while executed in conjunction with performing at least one of the system calls and TRAPs during ongoing processing system operation, can be rendered inapplicable during a selectable processing of the at least one of the system calls and TRAPs;

providing a slow instruction path and a fast instruction path;

placing the at least one of a pre-test and a post-test in the slow instruction path and excluding the at least one of a pre-test and a post-test from the fast instruction path;

designating a slow path flag that is capable of being set such that instructions in the slow instruction path will be executed during the at least one of the system calls and TRAPs, and that is capable of being cleared such that instructions in the fast instruction path will be executed during the at least one of the system calls and TRAPs.

27. A slow instruction path formed according to the method of claim 26.