Embedded configurable logic ASIC

• US 6,260,087 B1
• Filed: 03/03/1999
• Issued: 07/10/2001
• Est. Priority Date: 03/03/1999
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Web Chang
• Inventors: Chang, Web
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US09/261,244
• Time in Patent Office: 860 Days
• Field of Search: 710/126, 710/129, 710/131, 710/100, 710/104, 712/1, 712/32, 712/36, 712/41, 714/30, 714/33, 326/39, 326/40, 326/41, 345/503, 345/519
• US Class Current: 710/100
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified

Abstract

An Application Specific Integrated Circuit (“ASIC”) (10, 30 and 40), which includes at least one hardware, non-programmable functional block (12, 14, 16, 18, 22, 32, 44, 46 and 48), also includes a programmable logic block (“PLB”) (26). The PLB (26) is electrically programmable for performing at least one function that complements a function performed using the hardware, non-programmable functional block (12, 14, 16, 18, 22, 32, 44, 46 and 48). The presence of the PLB (26) in the ASIC providing system builders with an opportunity to readily differentiate products within their respective product lines by adding particular functions to the ASIC, and to also functionally differentiate among various products offered by competing system builders.

Claims

1. In an application specific integrated circuit (“

ASIC”

) that includes at least one hardware, non-programmable functional block adapted for performing a function, an improvement comprising;

a programmable logic block (“

PLB”

) included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable functional block.

2. The ASIC of claim 1 wherein the hardware, non-programmable functional block is a bus interface block.

3. The ASIC of claim 2 wherein the bus interface block is an Industry Standard Architecture (“

ISA”

) bus interface block.

4. The ASIC of claim 2 wherein the bus interface block is an Peripheral Component Interconnect (“

PCI”

) bus interface block.

5. The ASIC of claim 2 wherein the bus interface block is a Universial Serial Bus (“

USB”

) block^˜

.

6. The ASIC of claim 1 the ASIC is a PCI Bus Controller (“

PCIBC”

).

7. The ASIC of claim 6 wherein the hardware, non-programmable functional block of the PCIBC is a First-In/First-Out (“

FIFO”

) block, and a second hardware, non-programmable functional block included in the PCIBC is a processor block.

8. The ASIC of claim 7 wherein the processor block is a Reduced Instruction Set Computer (“

RISC”

) microprocessor.

9. The ASIC of claim 1 wherein the ASIC is a Smart Card Controller (“

SCC”

).

10. The ASIC of claim 9 wherein the hardware, non-programmable functional block of the SCC is a Serial Data I/O (“

SIO”

) block, and the SCC includes a second hardware, non-programmable functional block that is a processor block.

11. The ASIC of claim 10 wherein the processor block is a RISC microprocessor.

12. The ASIC of claim 1 wherein the ASIC is a RF Datacom Integrated Circuit (“

RFDIC”

).

13. The ASIC of claim 12 wherein the hardware, non-programmable functional block of the RFDIC is an Up/Down Frequency Converter block, and the RFDIC includes a second hardware, non-programmable functional block that is a processor block.

14. The ASIC of claim 13 wherein the processor block is a Digital Signal Processor (“

DSP”

).

15. The ASIC of claim 12 wherein the hardware, non-programmable functional block of the RFDIC is a Frequency-Hopping Spread-Spectrum Modulator/Demodulator block, and the RFDIC includes a second hardware, non-programmable functional block that is a processor block.

16. The ASIC of claim 15 wherein the processor block is a DSP.

17. The ASIC of claim 12 wherein the hardware, non-programmable functional block of the RFDIC is a Base-band Analog-to-Digital Converter (“

ADC”

) and Digital-to-Analog (“

DAC”

) block, and the RFDIC includes a second hardware, non-programmable functional block that is a processor block.

18. The ASIC of claim 17 wherein the processor block is a DSP.

19. The ASIC of claim 17 wherein the processor block is a RISC microprocessor.

20. An ASIC comprising:

a hardware, non-programmable functional block which is adapted for performing a functions; and

a PLB that is electrically programmable for performing, during normal operation of the ASIC, at least one function that complements a function performed by said hardware, non-programmable functional block.

21. In a PCIBC ASIC that includes at least:

a first hardware, non-programmable FIFO functional block; and

a second hardware, non-programmable processor functional block;

an improvement comprising;

a PLB included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable FIFO functional block.

22. The ASIC of claim 21 wherein the processor block is a RISC microprocessor.

23. In a SCC ASIC that includes at least:

a first hardware, non-programmable SIO functional block; and

a second hardware, non-programmable processor functional block;

an improvement comprising;

a PLB included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable SIO functional block.

24. The ASIC of claim 23 wherein the processor block is a RISC microprocessor.

25. In a RFDIC ASIC that includes at least:

a first hardware, non-programmable Up/Down Frequency Converter functional block; and

a second hardware, non-programmable processor functional block;

an improvement comprising;

a PLB included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable Up/Down Frequency Converter functional block.

26. The ASIC of claim 25 wherein the processor block is a DSP.

27. In a RFDIC ASIC that includes at least:

a first hardware, non-programmable Frequency-Hopping Spread-Spectrum Modulator/Demodulator functional block; and

a second hardware, non-programmable processor functional block;

an improvement comprising;

a PLB included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable Frequency-Hopping Spread-Spectrum Modulator/Demodulator functional block.

28. The ASIC of claim 27 wherein the processor block is a DSP.

29. In a RFDIC ASIC that includes at least:

a first hardware, non-programmable Base-band ADC and DAC functional block; and

a second hardware, non-programmable processor functional block;

an improvement comprising;

a PLB included in the ASIC, said PLB being electrically programmable for performing, during normal operation of the ASIC, at least one function that complements the function performed using the hardware, non-programmable Base-band ADC and DAC functional block.

30. The ASIC of claim 29 wherein the processor block is a DSP.

31. The ASIC of claim 29 wherein the processor block is a RISC microprocessor.