Method and apparatus for controlling a synchronous memory device

• US 6,260,097 B1
• Filed: 02/28/2000
• Issued: 07/10/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/514,872
• Time in Patent Office: 498 Days
• Field of Search: 710/100, 710/129, 710/35, 365/233, 365/235, 365/230.05
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of controlling a synchronous memory device comprising issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data. The first portion of data is provided to the memory device synchronously with respect to a rising edge transition of an external clock signal. A second portion of data is provided to the memory device synchronously with respect to a falling edge transition of the external clock signal. A memory controller for controlling a synchronous memory device comprises output driver circuitry to output data. The output driver circuitry outputs a first portion of data in response to a rising edge transition of the first external clock signal. In addition, the output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal.

Claims

1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data;

providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and

providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal.

2. The method of claim 1 wherein the write request includes an operation code.

3. The method of claim 2 wherein the memory device receives the operation code synchronously with respect to an edge transition of the external clock signal.

4. The method of claim 1 further including:

providing block size information to the memory device, wherein the block size information defines a first amount of data to be input by the memory device in response to a write request wherein;

a first portion of the first amount of data is sampled by the memory device in response to a rising edge transition of the external clock signal; and

a second portion of the first amount of data is sampled by the memory device in response to a falling edge transition of the external clock signal.

5. The method of claim 1 further including:

providing block size information to the memory device, wherein the block size information defines a first amount of data to be output by the memory device in response to a read request;

issuing a read request to the memory device; and

receiving the first amount of data from the memory device.

6. The method of claim 5 further including providing access time information to the memory device, wherein the access time information is representative of a number of clock cycles of the external clock signal to delay before the memory device outputs the first amount of data.

7. The method of claim 1 further including:

providing the external clock signal to the memory device wherein;

in response to a rising edge transition of the external clock signal the memory device samples the first portion of the data; and

in response to a falling edge transition of the external clock signal the memory device samples the second portion of the data.

8. A method of controlling a memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data;

providing a first portion of data to the memory device synchronously with respect to a first external clock signal; and

providing a second portion of data to the memory device synchronously with respect to a second external clock signal.

9. The method of claim 8 wherein the write request is included in a first packet, and the first portion of data and the second portion of data are included in a second packet.

10. The method of claim 8 wherein the write request includes an operation code.

11. The method of claim 8 further including:

providing block size information to the memory device, wherein the block size information defines a first amount of data to be input by the memory device in response to a write request; and

wherein a first portion of the first amount of data is sampled synchronously with respect to the first external clock signal, and a second portion of the first amount of data is sampled synchronously with respect to the second external clock signal.

12. The method of claim 8 further including:

providing block size information to the memory device, wherein the block size information defines a first amount of data to be output by the memory device in response to a read request; and

receiving the first amount of data from the memory device.

13. The method of claim 12 further including:

providing access time information to the memory device, wherein the access time information is representative of a number of clock cycles of the first external clock signal to delay before the memory device outputs data.

14. The method of claim 8 further including:

providing the first and second external clock signals to the memory device, wherein;

the first portion of data is sampled by the memory device synchronously with respect to the first external clock signal; and

the second portion of data is sampled by the memory device synchronously with respect to the second external clock signal.

15. The method of claim 14 wherein the first and second external clock signals are small voltage swing signals.

16. A memory controller for controlling a synchronous memory device, the memory controller comprising:

output driver circuitry to output data wherein;

the output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal; and

the output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal; and

multiplexer circuitry, coupled to the output driver circuitry, to provide the first and second portions of data to the output driver circuitry.

17. The memory controller of claim 16 wherein:

in response to the rising edge transition of the external clock signal, the multiplexer circuitry provides data to the output driver circuitry; and

in response to the falling edge transition of the external clock signal, the multiplexer circuitry provides data to the output driver circuitry.

18. The memory controller of claim 17 further including a delay lock loop circuit coupled to the external clock signal, the delay lock loop circuit generating a first internal clock signal, wherein the multiplexer circuitry couples the first portion of data to the output driver circuitry in response to the first internal clock signal.

19. The memory controller of claim 18 wherein the delay lock loop circuit generates a second internal clock signal, wherein the multiplexer circuitry couples the second portion of data to the output driver circuitry in response to the second internal clock signal.

20. The memory controller of claim 16 wherein both the rising edge transition of the first external clock signal and the falling edge transition of the external clock signal transpire in one clock cycle of the first external clock signal.

21. The memory controller of claim 16 wherein both the rising and falling edge transitions of the first external clock signal include voltage swings of less than one volt.

22. A memory controller for controlling a synchronous memory device, the memory controller comprising:

output driver circuitry to output data wherein;

the output driver circuitry outputs a first portion of data in response to a first external clock signal; and

the output driver circuitry outputs a second portion of data in response to a second external clock signal; and

multiplexer circuitry coupled to the output driver circuitry, to provide the first and second portions of data to the output driver circuitry.

23. The memory controller of claim 22, wherein:

in response to the first external clock signal, the multiplexer circuitry provides data to the output driver circuitry; and

in response to the second external clock signal, the multiplexer circuitry provides data to the output driver circuitry.

24. The memory controller of claim 22 further including a delay lock loop circuit coupled to the first external clock signal, the delay lock loop circuit generating a first internal clock signal, wherein the multiplexer circuitry couples the first portion of data to the output driver circuitry in response to the first internal clock signal.

25. The memory controller of claim 24 wherein the delay lock loop circuit generates a second internal clock signal, wherein the multiplexer circuitry couples the second portion of data to the output driver circuitry in response to the second internal clock signal.

26. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

providing first block size information to the memory device, wherein the first block size information defines an amount of data to be input by the memory device in response to a write request;

issuing the write request to the memory device, wherein the memory device samples the write request synchronously with respect to an external clock and, in response to the write request, the memory device samples first and second portions of data;

providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and

providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal.

27. The method of claim 26 wherein the write request is included in a first packet and both the first and second portions of data are included in a second packet.

28. The method of claim 26 wherein the write request includes an operation code.

29. The method of claim 28 wherein the memory device samples the operation code synchronously with respect to a first transition of the external clock signal.

30. The method of claim 26 wherein:

a first portion of the amount of data is sampled by the memory device in response to a rising edge transition of the external clock signal; and

a second portion of the amount of data is sampled by the memory device in response to a falling edge transition of the external clock signal.

31. The method of claim 26 wherein the first block size information and the write request are included in a packet.

32. The method of claim 26 further including:

providing second block size information to the memory device, wherein the second block size information defines an amount of data to be output by the memory device in response to a read request;

issuing a first read request to the memory device; and

receiving the amount of data output by the memory device.

33. The method of claim 26 further including providing access time information to the memory device, wherein the access time information is representative of a number of clock cycles of the external clock signal to transpire before the memory device outputs data.

34. The method of claim 26 further including providing the external clock signal to the memory device wherein:

in response to a first edge transition of the external clock signal the memory device samples the first portion of the data; and

in response to a second edge transition of the external clock signal the memory device samples the second portion of the data, wherein the first and second edge transitions are from the same clock cycle of the external clock signal.

35. The method of claim 26 wherein the external clock signal is provided by an external clock generator.