Foreground and background context controller setting processor to power saving mode when all contexts are inactive

• US 6,260,150 B1
• Filed: 12/17/1998
• Issued: 07/10/2001
• Est. Priority Date: 03/10/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Diepstraten, Wilhelmus J. M., Fischer, Michael A., Hardell, Wesley D.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/213,102
• Time in Patent Office: 936 Days
• Field of Search: 709/108, 709/107, 712/228, 712/229, 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively, and (2) mode switching circuitry, coupled to the foreground and background task controllers, that places the processor in an idle state and a power saving mode when all of the contexts are inactive.

Claims

1. A context controller for managing multitasking in a processor, comprising:

foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively; and

mode switching circuitry, coupled to said foreground and background task controllers, that places said processor in an idle state and a power saving mode when all of said contexts are inactive.

2. The context controller as recited in claim 1 wherein a software switch state distinguishes said foreground tasks from said background tasks.

3. The context controller as recited in claim 1 wherein said foreground and background task controllers allocate said processor resources only to said active contexts.

4. The context controller as recited in claim 1 wherein said background task controller activates said contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks.

5. The context controller as recited in claim 1 wherein said contexts are stored in separate register sets.

6. The context controller as recited in claim 1 wherein said foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to events and said background task controller cyclicly activates contexts corresponding to background tasks subject to activation of said contexts corresponding to said foreground tasks.

7. The context controller as recited in claim 1 wherein said foreground task controller is adapted to activate a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

8. A method of managing multitasking in a processor, comprising the steps of:

allocating processor resources to active contexts corresponding to foreground and background tasks, respectively; and

placing said processor in an idle state and a power saving mode when all of said contexts are inactive.

9. The method as recited in claim 8 wherein a software switch state distinguishes said foreground tasks from said background tasks.

10. The method as recited in claim 8 wherein said foreground and background task controllers allocate said processor resources only to said active contexts.

11. The method as recited in claim 8 wherein said background task controller activates said contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks.

12. The method as recited in claim 8 wherein said contexts are stored in separate register sets.

13. The method as recited in claim 8 wherein said foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to events and said background task controller cyclicly activates contexts corresponding to background tasks subject to activation of said contexts corresponding to said foreground tasks.

14. The method as recited in claim 8 wherein said foreground task controller is adapted to activate a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

15. A processor, comprising:

an instruction decoder that decodes instructions received into said processor and corresponding to a plurality of tasks;

a plurality of register sets, corresponding to said plurality of tasks, that contain operands to be manipulated;

an execution core, coupled to said instruction decoder and said plurality of register sets, that executes instructions corresponding to an active one of said plurality of tasks to manipulate ones of said operands; and

a context controller, coupled to said instruction decoder and said execution core, that manages multitasking with respect to said plurality of tasks, including;

foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively, and

mode switching circuitry, coupled to said foreground and background task controllers, that places said processor in an idle state and a power saving mode when all of said contexts are inactive.

16. The processor as recited in claim 15 wherein a software switch state distinguishes said foreground tasks from said background tasks.

17. The processor as recited in claim 15 wherein said foreground and background task controllers allocate said processor resources only to said active contexts.

18. The processor as recited in claim 15 wherein said background task controller activates said contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks.

19. The processor as recited in claim 15 wherein said contexts are stored in separate register sets.

20. The processor as recited in claim 15 wherein said foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to events and said background task controller cyclicly activates contexts corresponding to background tasks subject to activation of said contexts corresponding to said foreground tasks.

21. The processor as recited in claim 15 wherein said foreground task controller is adapted to activate a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

22. The processor as recited in claim 15 wherein said processor forms a portion of a general-purpose computer.