Semiconductor integrated circuit device, and fabrication process and designing method thereof

• US 6,261,883 B1
• Filed: 03/31/1998
• Issued: 07/17/2001
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamada, Youhei, Moniwa, Masahiro, Nagasawa, Koichi, Koubuchi, Yasushi, Takeda, Toshifumi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/050,416
• Time in Patent Office: 1,204 Days
• Field of Search: 438/622, 438/926, 438/197, 438/198, 438/201, 438/212, 257/758, 257/776, 257/752
• US Class Current: 438/197
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Claims

1. A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

patterning a conductive film deposited on a semiconductor substrate to form interconnections and dummy interconnections;

embedding a concave portion, defined by said interconnections and dummy interconnections, with a first insulating film such that the film thickness in said concave portion becomes larger than the thickness on said interconnections and dummy interconnections;

depositing a second insulating film over said first insulating film; and

polishing the surface of said second insulating film,

wherein said dummy interconnections are formed respectively between adjacent interconnections, wherein said dummy interconnections, formed between said adjacent interconnections, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy interconnections are located so as to be regularly repeated between said adjacent interconnections.

2. A process according to claim 1,

wherein the dummy interconnections are formed on a dummy region of the semiconductor substrate, and wherein the width of said dummy region is at least twice the minimum line width required by the resolution power of lithography.

3. A process according to claim 1,

wherein the distance between adjacent members of said dummy interconnections is not greater than twice the height of said interconnections.

4. A process according to claim 1,

wherein said dummy interconnections are formed also in a scribing area.

5. A process according to claim 1,

wherein said dummy interconnections are not formed, in the same interconnection layer with that of a bonding pad portion or a marker portion for photolithography, at the periphery of said bonding pad portion or marker portion.

6. A process according to claim 1, wherein said interconnections serve as gate electrodes of MISFETs.

7. A process according to claim 1, further comprising the steps of:

etching said semiconductor substrate to form a trench in a region defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;

forming a third insulating film over said trench, active regions and dummy regions; and

polishing said third insulating film to embed said trench with said third insulating film.

8. A process according to claim 7, wherein said interconnections serve as gate electrodes of MISFETs formed over said active region, and wherein said dummy interconnections are formed over said third insulating film and are electrically isolated from said MISFETs.

9. A process according to claim 8, wherein said interconnections extend over said active region and said third insulating film;

and wherein said interconnections are formed not to extend over said dummy regions.

10. A process according to claim 8, wherein said dummy interconnections extend over said dummy regions and said third insulating film.

11. A method of according to claim 7, wherein said dummy regions are formed in a scribing area.

12. A process according to claim 1, wherein said polishing step is performed by a chemical mechanical polishing method.

13. A process according to claim 1, wherein each of said dummy interconnections has a rectangular shape.

14. A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

etching a semiconductor substrate to form a trench in regions defining active regions and dummy regions;

depositing an insulating film over said active regions, dummy regions and trench; and

polishing said insulating film to embed said trench with said insulating film;

a distance between adjacent dummy and active regions being not greater than twice the depth of said trench, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions.

15. A process according to claim 14,

wherein the width of said dummy region is at least twice the minimum line width required by the resolution power of lithography.

16. A process according to claim 14, wherein MISFETs are not formed in said dummy region.

17. A method according to claim 16, wherein said dummy interconnections are not formed at the peripheral portion of a marker portion for photolithography.

18. A process according to claim 14, further comprising the steps of:

forming a gate interconnection and dummy interconnection by patterning a conductive film formed over said active and, dummy regions and insulating film,

wherein said gate interconnection serves as a gate electrode of an MISFET formed over said active region, and

wherein said dummy interconnection is formed over said insulating film.

19. A process according to claim 18, wherein said gate interconnection extends over said active region and said insulating film, and

wherein said gate interconnection is formed not to extend over said dummy regions.

20. A process according to claim 18, further comprising the steps of:

forming a further insulating film over said gate interconnection and dummy interconnection; and

polishing said further insulating film.

21. A process according to claim 14, wherein said polishing step is performed by a chemical mechanical polishing method.

22. A process according to claim 14, wherein each of said dummy regions has a shape with four sides.

23. A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

etching a semiconductor substrate to form a trench in regions defining active regions and dummy regions;

depositing an insulating film on said active regions, dummy regions and trench; and

polishing said insulating film to embed said trench with said insulating film;

the width of said dummy regions being at least twice the minimum line width required by the resolution power of lithography, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions.

24. A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

etching a silicon nitride film deposited on the principal surface of a semiconductor substrate and etching said semiconductor substrate to form a trench in regions defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;

depositing an insulating film over said active and dummy regions and trench;

polishing said insulating film using an alkaline slurry which contains a silicon oxide as an abrasive to embed said trench with said insulating film; and

subsequent to said polishing step, etching said insulating film formed in said trench to make the height of the surface of said insulating film equal to or lower than the principal surface of said semiconductor substrate.

25. A process for fabricating a semiconductor integrated circuit device, comprising the steps of:

etching a silicon nitride film deposited on the principal surface of a semiconductor substrate and etching said semiconductor substrate to form a trench in regions defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;

depositing an insulating film over said active and dummy regions and trench; and

polishing said insulating film using cerium oxide as an abrasive to embed said trench with said insulating film.

26. A designing method of a mask pattern of a mask used for the processing of members constituting a semiconductor integrated circuit device, including:

forming the mask pattern, wherein said mask pattern is formed so that in a region of at least 95% of a chip, pattern distance between patterns of said members and dummy patterns is not greater than twice the height of said members and in a region not greater than 5% of said chip, said pattern distance is not greater than four times the height of said members.

27. A method according to claim 26,

wherein said dummy patterns are disposed also in a scribing area of a semiconductor substrate.

28. A method according to claim 26,

wherein said dummy patterns are not disposed in a dummy placement prohibited region;

and

said dummy placement prohibited region includes at least one of the periphery of a pattern to be a bonding pad, the periphery of a pattern to be a marker of photolithography and a fuse region.

29. A method according to claim 26,

wherein said dummy patterns are not disposed in a dummy placement prohibited region;

a region above a storage capacitative element of a memory cell becomes said dummy placement prohibited region.

30. A method according to claim 26,

wherein said dummy patterns are not disposed in a dummy placement prohibited region;

a region, where a gate interconnection is formed, on the principal surface of a semiconductor substrate becomes said dummy placement prohibited region.

31. A method according to claim 26,

wherein said dummy patterns are disposed so as to minimize an increase of a floating capacitance caused by dummy members formed through said dummy patterns.

32. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:

etching a semiconductor substrate to form a trench in a region defining active regions and dummy regions, wherein said dummy regions are formed respectively between adjacent active regions, wherein said dummy regions, formed between the adjacent active regions, are of the same size in width and length and are separated from each other by a distance, and wherein said dummy regions are located so as to be regularly repeated between said adjacent active regions;

forming a first insulating film over said trench, active regions and dummy regions;

polishing said first insulating film to embed said trench with said first insulating film; and

forming gate interconnections and dummy interconnections by patterning a conductive film formed over said active regions, dummy regions and first insulating film, wherein said dummy interconnections are formed respectively between adjacent gate interconnections, wherein said dummy interconnections, formed between said adjacent gate interconnections, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy interconnections are located so as to be regularly repeated between si adjacent gate interconnections,

wherein said gate interconnections serve as gate electrodes of MISFETs formed over said active regions, and

wherein said dummy interconnections are formed over said first insulating film.

33. A method according to claim 32, wherein MISFETs are not formed in said dummy regions.

34. A method according to claim 33, wherein said dummy interconnections are electrically-isolated from said MISFETs.

35. A method according to claim 32 wherein said dummy interconnections are electrically isolated from said MISFETs.

36. A method according to claim 32, wherein said gate interconnections extend over said active regions and said first insulating film, and wherein said gate interconnections are formed not to extend over said dummy regions.

37. A method according to claim 32, further comprising the steps of:

forming a second insulating film over said gate interconnections and dummy interconnections; and

polishing said second insulating film.

38. A method according to claim 37, wherein said polishing steps of the first and second insulating films are performed by a chemical mechanical polishing method.

39. A method according to claim 32, wherein said dummy regions are formed in a scribing area.

40. A method according to claim 32, wherein said dummy interconnections are not formed at the peripheral portion of a marker portion for photolithography.

41. A method of fabricating a semiconductor integrated circuit device, comprising the steps of:

forming in a semiconductor substrate an element isolation region defining active regions;

forming gate interconnections and dummy interconnections by patterning a conductive film formed over said semiconductor substrate, wherein said dummy interconnections are formed respectively between adjacent gate interconnections, wherein said dummy interconnections, formed between said adjacent gate interconnections, are of a same size in width and length and are separated from each other by a distance, and wherein said dummy interconnections are located so as to be regularly repeated between said adjacent gate interconnections;

forming a first insulating film over said gate interconnections and dummy interconnections; and

polishing said first insulating film,

wherein said gate interconnections serve as gate electrodes of MISFETs formed over said active regions, and

wherein said dummy interconnections are formed over said element isolation region.

42. A method according to claim 41, wherein the semiconductor substrate includes dummy regions, and wherein MISFETs are not formed in said dummy regions.

43. A method according to claim 41, wherein said dummy interconnections are electrically isolated from said MISFETs.

44. A method according to claim 41, wherein said dummy interconnections are not formed at the peripheral portion of a marker portion for photolithography.

45. A method according to claim 41, wherein said polishing step is performed by a chemical mechanical polishing method.

46. A method according to claim 41, wherein said element isolation region includes a trench and a second insulating film formed in said trench such that said trench defines said active regions and dummy regions.

47. A method of fabricating a semiconductor integrated circuit device including metal insulator semiconductor field effect elements, comprising the steps of:

(a) providing a semiconductor substrate having a principal surface, said principal surface including active areas for said elements to be formed, and an isolation area for providing a required space between said active areas;

(b) forming a trench pattern in said semiconductor substrate except for said active areas, thereby to form a plurality of dummy semiconductor regions, separated from each other by said trench pattern, at said isolation area,

said trench pattern having a selected trench portion formed at a portion of said isolation area where a gate interconnection for said elements is to be provided, and having another trench portion formed so as to define active semiconductor regions at said active areas,

said dummy semiconductor regions being of the same size in width and length as each other and being located so as to be regularly repeated at said isolation area;

(c) depositing a first insulating film over said principal surface of the semiconductor substrate having said trench pattern;

(d) removing said first insulating film from said principal surface to embed a resultant first insulating film in said trench pattern;

(e) forming a first conductive film over gate insulating films, which are formed on said active semiconductor regions and said dummy semiconductor regions, and said resultant first insulating film embedded in said trench pattern;

(f) patterning said first conductive film thereby to form gate electrodes over said gate insulating films covering said active semiconductor regions, and to form a gate interconnection over the selected portion of said trench pattern at said isolation area;

(g) applying a flattened second insulating film over all areas of said active areas and said isolation area; and

(h) forming interconnections extending on said second insulating film by patterning a second conductive film formed over said second insulating film.

48. A method of fabricating a semiconductor integrated circuit device including metal insulator semiconductor field effect elements, comprising the steps of:

(a) providing a semiconductor substrate having a principal surface, said principal surface including active areas for said elements to be formed, and an isolation area for providing a required space between said active areas;

(b) forming a trench pattern in said semiconductor substrate except for said active areas, thereby to form a plurality of dummy semiconductor regions, separated from each other by said trench pattern, at said isolation area,

said trench pattern having a selected trench portion formed at a portion of said isolation area where a gate interconnection for said elements is to be provided, and having another trench portion formed so as to define active semiconductor regions at said active areas;

said dummy semiconductor regions being of the same size in width and length as each other and being located so as to be regularly repeated at said isolation area;

(c) depositing a first insulating film over said principal surface of the semiconductor substrate having said trench pattern;

(d) removing said first insulating film from said principal surface to embed a resultant first insulating film in said trench pattern;

(e) forming a first conductive film over gate insulating films, which are formed on said active semiconductor regions and said dummy semiconductor regions, and over said resultant first insulating film embedded in said trench pattern;

(f) patterning said first conductive film thereby to form gate electrodes over said gate insulating films covering said active semiconductor regions, to form a gate interconnection over said selected portion of the trench pattern at said isolation area, and to form dummy interconnections over said gate insulating films covering said dummy semiconductor regions,

said dummy interconnections being under an electrically floating state;

(g) applying a flattened second insulating film over all areas of said active areas and said isolation area; and

(h) forming interconnections extending on said second insulating film by patterning a second conductive film formed over said second insulating film.

49. A method according to claim 48, wherein said dummy interconnections are formed over said gate insulating films covering said dummy semiconductor regions and over trench portions of said trench pattern which are located between adjacent dummy semiconductor regions, wherein said dummy interconnections are of the same size in width and length as each other, and wherein said dummy interconnections are located so as to be regularly repeated at said isolation area.

50. A method according to claim 49, wherein each of said dummy semiconductor regions and said dummy interconnections has a shape with four sides.

51. A method according to claim 49, wherein each of said dummy semiconductor regions and said dummy interconnections has a square shape.

52. A method according to claim 49, wherein each of said dummy semiconductor regions and said dummy interconnections has a rectangular shape.

53. A method according to claim 49, wherein said dummy interconnections include at least a first group of a first same size and a second group of a second same size different from said first same size.

54. A method according to claim 53, wherein each of said first and second groups of said dummy interconnections has a rectangular shape.