Producing microstructures or nanostructures on a support

• US 6,261,928 B1
• Filed: 02/22/2000
• Issued: 07/17/2001
• Est. Priority Date: 07/22/1997
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Bruel, Michel
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/463,226
• Time in Patent Office: 511 Days
• Field of Search: 438/406, 438/455, 438/458, 438/459, 438/478, 148/33, 148/DIG.3, 156/153
• US Class Current: 438/459
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/185 Joining of semiconductor bodies for junction formation
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31

Abstract

A method for producing a micro- or nanostructure on a substrate. In a first step, one surface of a first wafer in crystalline material is placed in contact with one surface of a second wafer in crystalline material, such that crystalline lattices presented by the surfaces offer at least one mismatch parameter able to allow the formation of a lattice of crystalline defects and/or of a lattice of strains within a crystalline zone extending on either side of the interface of the two wafers, at least one of the lattices determining the micro- or nanostructure. Then, one of the two wafers is thinned to expose the lattice defects and/or the lattice strains on a substrate formed by the other wafer.

Claims

1. A method for producing a micro or nanostructure on a substrate, comprising the steps of:

bonding by placing one surface of a first wafer in crystalline material in contact with one surface of a second wafer in crystalline material, such that the crystalline lattices presented by said surfaces offer at least one mismatch parameter able to allow the formation of a lattice of crystalline defects and/or a lattice of strains within a crystalline zone extending either side of the interface of the two wafers, at least one of said lattices determining the micro or nanostructure,

thinning one of the two wafers to expose the lattice defects and/or lattice strains on a substrate formed by the other wafer,

selective treatment of the lattice crystalline defects and/or lattice strains in relation to said crystalline zone, or vice versa.

2. Method according to claim 1, in which said mismatch parameter is formed by a determined angle of rotational shift in the crystalline lattices presented by said surfaces.

3. Method according to claim 1, in which said mismatch parameter is formed by a difference in crystalline mesh parameter between the crystalline materials of the contacted surfaces of the wafers.

4. Method according to claim 1, in which said mismatch parameter is formed by a determined angle according to which the surface of at least one of the wafers is shifted in relation to the ordinary crystallographic plane direction corresponding to this surface.

5. Method according to claim 1, in which the contacting is of hydrophobic type.

6. Method according to claim 1, in which the contacting is of hydrophilic type.

7. Method according to claim 1, in which, during the contacting step, the first wafer and second wafer are submitted to at least one of the following operations:

heat treatment, pressurizing, application of an electric field.

8. Method according to claim 1, also comprising at least one heat treatment step intended to complete or end the formation of the lattice of crystalline defects and/or lattice strains.

9. Method according to claim 1, in which the thinning step is conducted by means of a technique chosen from among grinding, mechanical polishing or chemical polishing.

10. Method according to claim 1, in which the thinning step is conducted by cleavage of one of the wafers which, before the contacting step, is subjected via its contacting surface to an ion implantation step intended, at a determined depth corresponding to the required thinning, to create a layer of microcavities able to generate a cleavage plane during a subsequent heat treatment step.

11. Method according to claim 10, in which ion implantation is made by means of hydrogen ions.

12. Method according to claim 10, in which at least one heat treatment step is planned making it possible simultaneously to complete or end the formation of a lattice of crystalline defects and/or lattice of strains and to generate the cleavage plane.

13. Method according to claim 1, in which the selective treatment step comprises making conductive the crystalline defects and/or lattice strains such that said crystalline zone forms crystalline pads electrically connected to one another.

14. Method according to claim 13, in which the crystalline defects are made conductive by phosphorus diffusion.

15. Method according to claim 1, in which the selective treatment step comprises electric insulation so that said crystalline zone forms crystalline pads electrically insulated from one another.

16. Method according to claim 15, in which the selective treatment comprises chemically polishing the crystalline defects and/or lattice strains.

17. Method according to claim 16, in which said chemical polishing is preceded by a decoration phase of the crystalline defects and/or lattice strains by precipitation of metallic or doping impurities.

18. Method according to claim 16, in which chemical polishing is followed by the depositing of an electric insulator.

19. Method according to claim 15, in which said electric insulation is of the type in which electric conduction may take place therein by means of a physical effect such as the tunneling effect or the Fowler-Nordheim effect.

20. Method according to claim 1, in which the selective treatment step comprises treating the crystalline defects and/or lattice strains such that said crystalline zone forms crystalline pads connected together by semiconductor zones or having a potential barrier.

21. Method according to claim 1, in which the selective treatment step comprises depositing, by epitaxy, a crystalline material having crystalline mesh mismatch with the crystalline material exposed by the thinning step, this deposited crystalline material forming an arranged set of islands corresponding to the lattice of crystalline defects and/or underlying lattice strains.

22. Micro or nanostructure on a substrate, obtained according to claim 1, from wafers whose contacting surfaces are in semiconductor material, the crystalline lattices presented by said surfaces offering at least one mismatch parameter allowing the formation of a lattice of crystalline defects and/or lattice of strains from which arises said micro- or nanostructure.

23. Micro or nanostructure on a substrate according to claim 22, in which at least one of said contacting surfaces is in SiC.

24. Micro or nanostructure on a substrate according to claim 22, in which at least one of said contacting surfaces is in III-V semiconductor material such as AsGa or GaAlAs.

25. Micro or nanostructure on a substrate, obtained according to claim 1, one of the wafers being formed by a Silicon-On-Insulator wafer, the other wafer being in silicon and forming the thinned wafer, the method enabling a micro or nanostructure to be obtained made up of silicon microvolumes on an insulator layer.