Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect

• US 6,261,944 B1
• Filed: 11/24/1998
• Issued: 07/17/2001
• Est. Priority Date: 11/24/1998
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantiss (Lattice Semiconductor Corporation)
• Inventors: Mehta, Sunil D., Li, Xiao-Yu
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/200,395
• Time in Patent Office: 966 Days
• Field of Search: 438/626, 438/631, 438/632, 438/633, 438/634, 438/645, 438/646, 438/697, 438/698, 438/699, 438/758, 438/760, 438/782, 438/958, 438/624, 438/106, 438/612, 438/614, 438/617
• US Class Current: 438/624
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.

Claims

1. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a plurality of patterned metal layers thereon, wherein each of the patterned metal layers is separated by a dielectric layer;

forming a plasma oxide layer overlying the plurality of patterned metal layers;

forming a planarization layer overlying the plasma oxide layer;

applying thermal energy to anneal the planarization layer;

removing a portion of the planarization layer to form a substantially flat surface;

hardening the planarization layer, after removing the portion of the planarization layer;

forming a plasma oxide layer overlying the planarization layer; and

forming a plasma nitride layer overlying the plasma oxide layer.

2. The method of claim 1 further comprising the step of hardening the planarization layer prior to removing a portion of the planarization layer.

3. The method of claim 2, wherein the step of hardening the planarization layer comprises ion implanting a dopant species into the planarization layer.

4. The method of claim 3, wherein the step of ion implanting a dopant species comprises ion implanting a dopant series selected from the group consisting of arsenic and phosphorus.

5. The method of claim 1, wherein the step of forming a planarization layer comprises spin coating a liquid material onto the plasma oxide layer.

6. The method of claim 5, wherein the step of spin coating a liquid material comprises spin coating a siloxane material.

7. The method of claim 1, wherein the step of hardening the planarization layer comprises ion implanting a dopant species into the planarization layer.

8. The method of claim 7, wherein the step of ion implanting a dopant species comprises ion implanting a dopant species.

9. A method for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having a device layer thereon, and having an interconnect layer overlying the device layer,

wherein the interconnect layer is characterized by uneven surface regions;

forming a stress relieving layer overlying the interconnect layer;

spin coating a glass material onto the stress relieving layer to form a uniform layer;

removing a surface portion of the uniform layer;

hardening the uniform layer after removing the surface portion;

forming a protection layer overlying the planarized layer; and

forming openings through the protection layer, the planarized layer, and the stress relieving layer to expose contact surface regions on the interconnect layer.

10. The method of claim 9, wherein the step of spin coating a glass material comprises the steps of:

providing a siloxane liquid; and

dispensing the siloxane liquid onto the semiconductor substrate to form a uniform layer overlying the stress relieving layer.

11. The method of claim 9 further comprising the step of curing the uniform layer.

12. The method of claim 11 wherein the step of hardening the planarized layer comprises the step of introducing a dopant into the uniform layer to harden the uniform layer.

13. The method of claim 9, wherein the step of removing a surface portion of the uniform layer comprises the step of plasma etching the surface portion of the uniform layer to form a planarized layer.

14. A method for fabricating high-density passivation layers in a semiconductor device, wherein the semiconductor device includes a device layer and a multi-level interconnect layer overlying the device layer, and wherein the multi-level interconnect layer is characterized by uneven surface regions, the method comprising the steps of:

forming a stress relieving layer overlying the multi-level interconnect layer;

forming a planarization layer overlying the stress relieving layer;

removing surface portions of the planarization layer and the stress relieving layer to form a substantially smooth surface hardening the planarization layer after removing the surface portion of the planarization layer; and

forming at least one passivation layer overlying the substantially smooth surface.

15. The method of claim 14, wherein the step of forming a planarization layer comprises spin coating a glass material onto the stress relieving layer to form a uniform layer.

16. The method of claim 15, wherein the step of spin coating a glass material comprises the steps of:

providing a siloxane liquid; and

dispensing the siloxane liquid onto the semiconductor substrate.

17. The method of claim 15 further comprising the step of curing the uniform layer.

18. The method of claim 17 further comprising the step of hardening the uniform layer by introducing a dopant into the uniform layer.

19. The method of claim 14, wherein the step removing surface portions of the planarization layer and the stress relieving layer comprises a process selected from the group consisting of plasma etching and CMP.

20. The method of claim 14, wherein the step of forming a stress relieving layer comprises PECVD of silicon oxide.

21. The method of claim 14, wherein the step of forming at least one passivation layer comprises PECVD of silicon oxide.

22. The method of claim 14 further comprising the step of forming openings through the at least one passivation layer, the planarized layer, and the stress relieving layer to expose bond pad regions on the multi-level interconnect layer.

23. The method of claim 14 further comprising the step of introducing phosphorus into the at least one passivation layer.