Method for manufacturing semiconductor device

• US 6,261,949 B1
• Filed: 04/06/1999
• Issued: 07/17/2001
• Est. Priority Date: 04/07/1998
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Sukekawa, Mitsunari
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/286,704
• Time in Patent Office: 833 Days
• Field of Search: 438/634, 438/627, 438/643, 438/637, 438/648, 438/624, 438/638, 438/618, 438/622, 438/623, 257/750, 257/751, 257/758
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics

Abstract

A contact hole is formed in the first interlayer insulation film on a semiconductor substrate. While making the contact hole remaining a cavity, the second interlayer insulation film is formed on the first interlayer insulation film. Thereafter, a resist film having a wiring groove pattern is formed on the second interlayer insulation film. Using this resist film as a mask, the second interlayer insulation film is etched. By so doing, a wiring groove is formed in the second interlayer insulation film, and the contact hole which remains a cavity is opened, thereby forming a wiring groove and a contact hole substantially simultaneously. A nitride film formed between the first interlayer insulation film and the second interlayer insulation film may, therefore, merely function as an etching stopper. Thus, it is possible to either make the nitride film thinner than the conventional nitride film or to dispense with the nitride film. Hence, it is possible to reduce the capacity of the interlayer wiring.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a first interlayer insulation film on a conductive material;

forming an etching stopper film on said first interlayer insulation film;

forming a first photoresist film on said etching stopper film;

forming a contact hole in said first photoresist film to expose said etching stopper film;

then forming a contact hole in said etching stopper film and said first interlayer insulation film to expose the conductive material;

forming a second interlayer insulation film on said first interlayer insulation film while making said contact hole remain as a cavity;

forming a second resist film for a wiring groove pattern on said second interlayer insulation film;

forming a wiring groove in said second interlayer insulation film by etching said second interlayer insulation film with said second resist film used as a mask and thereby opening the contact hole confined by said second interlayer insulation film; and

forming a wiring and a contact by embedding metal material into said wiring groove and said contact hole.

2. The method according to claim 1, wherein an etching end point of said first interlayer insulation film is detected by detecting etching of said stopper film.

3. The method according to claim 1, wherein the metal material embedded into said contact hole and wiring groove is a laminated film consisting of Ti and TiN and a tungsten film.

4. The method according to claim 1, wherein said second interlayer insulation film is a silicon oxide film.

5. The method according to claim 1, wherein said first interlayer insulation film is a BPSG film.

6. A method for manufacturing a semiconductor device comprising the steps of:

forming a first interlayer insulation film on a conductive material;

forming a first resist film on said first interlayer insulation film;

forming a contact hole pattern on said first resist film;

then forming a contact hole in said first interlayer insulation film by etching said first interlayer insulation film with said first resist film used as a mask;

forming a second interlayer insulation film on said first interlayer insulation film while making said contact hole remain a cavity;

forming a second resist film on said second interlayer insulation film;

forming a wiring groove pattern on said second resist film;

forming a wiring groove in said second interlayer insulation film by etching said second interlayer insulation film with said second resist used as a mask, and opening the contact hole confined by said second interlayer insulation film; and

forming a wiring and a contact by embedding metal material into said wiring groove and said contact hole.

7. The method according to claim 6, comprising the step of, between the step of forming said first interlayer insulation film and the step of forming said first resist film, forming a stopper film on said first interlayer insulation film.

8. The method according to claim 7, wherein said contact hole is formed by continuously etching said stopper film and said first interlayer insulation film with said first resist film used as a mask.

9. The method according to claim 8, wherein an etching end point of said first interlayer insulation film is detected by detecting etching of said stopper film.

10. The method according to claim 6, wherein the metal material embedded into said contact hole and wiring groove is a laminated film consisting of Ti and TiN and a tungsten film.

11. The method according to claim 6, wherein said second interlayer insulation film is a silicon oxide film.

12. The method according to claim 6, wherein said first interlayer insulation film is a BPSG film.

13. A method for manufacturing a semiconductor device comprising the steps of:

forming a first interlayer insulation film on a conductive material;

forming a contact hole in said first interlayer insulation film to expose said conductive material;

then, forming a second interlayer insulation film on said first interlayer insulation film while making said contact hole remain as a cavity;

forming a resist film for a wiring groove pattern on said second inlayer insulation film;

forming a wiring groove in said second interlayer insulation film by etching said second interlayer insulation film with said resist film used as a mask, and opening the contact hole confined by said second interlayer insulation film; and

forming a wiring and a contact by embedding metal material into said wiring groove and said contact hole.