Silicon carbide semiconductor device

• US 6,262,439 B1
• Filed: 11/27/1998
• Issued: 07/17/2001
• Est. Priority Date: 11/28/1997
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamamoto, Tsuyoshi, Takeuchi, Yuichi
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US09/200,701
• Time in Patent Office: 963 Days
• Field of Search: 257/77, 257/341, 257/339, 257/356, 257/331
• US Class Current: 257/77
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor substrate includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer thereon. A first conductivity type semiconductor region is formed in a surface portion of the second conductivity type semiconductor layer and is divided into first and second regions. A trench is formed in the semiconductor substrate so as to penetrate the second conductivity type semiconductor layer and to reach the first conductivity type semiconductor layer. The first region is disposed around the trench so that the side surface of the first region is exposed to the trench. The second region is disposed to be distant from the trench and to be adjacent to the first region. A bottom face of the second region is located to a position deeper than that of said first region. As a result, when a high voltage is applied between a source and a drain, it is possible to cause a punch-through phenomenon to occur at the second region earlier than at the first region.

Claims

1. A silicon carbide semiconductor device comprising:

a semiconductor substrate made of single crystal silicon carbide, in which a first conductivity type second semiconductor layer and a second conductivity type third semiconductor layer are successively deposited on a first conductivity type first semiconductor layer, said second semiconductor layer having a resistance value higher than said first semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said third semiconductor layer and to reach said second semiconductor layer;

a first conductivity type semiconductor region formed in a surface portion of said third semiconductor layer, wherein said semiconductor region is divided into first and second regions, said first region is disposed around said trench so that a side surface of said first region is exposed to said trench, and said second region is disposed to be distant from said trench and to be adjacent to said first region;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

an interlayer insulation film formed on said gate electrode to cover said gate electrode;

a first electrode layer formed on said interlayer insulation layer and electrically connected to said second region; and

a second electrode layer electrically connected to said first semiconductor layer,

wherein a thickness of said third semiconductor layer between said second region and said second semiconductor layer is made thinner than that of said third semiconductor layer between said first region and said second semiconductor layer.

2. The silicon carbide semiconductor device according to claim 1, wherein said second region is formed by ion implantation using said interlayer insulation film as a mask.

3. The silicon carbide semiconductor device according to claim 2, wherein said interlayer insulation film has a thickness by which ions implanted for forming said second region are blocked.

4. The silicon carbide semiconductor device according to claim 1, wherein a bottom surface of said second region is located to a position deeper than that of said first region.

5. The silicon carbide semiconductor device according to claim 4, wherein said third semiconductor layer has a stepped portion on its surface so that a surface of said third semiconductor layer in a region for said first region to be formed is made higher than that in a region for said second region to be formed.

6. A silicon carbide semiconductor device comprising:

a semiconductor substrate made of single crystal silicon carbide, in which a first conductivity type second semiconductor layer and a second conductivity type third semiconductor layer are successively deposited on a first conductivity type first semiconductor layer, said second semiconductor layer having a resistance value higher than said first semiconductor layer;

a first conductivity type first region made of semiconductor formed in a surface portion of said third semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said first region and said third semiconductor layer and to reach said second semiconductor layer;

a second region made of metal silicide and metal carbide and formed in said third semiconductor layer so that a part of said third semiconductor layer is disposed between a bottom surface of said second region and a top surface of said second semiconductor layer in contact with said bottom surface of said second region, wherein said second region is disposed to be distant from said trench and to be adjacent to said first region;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

an interlayer insulation film formed on said gate electrode to cover said gate electrode;

a first electrode layer formed on said interlayer insulation layer and electrically connected to said second region; and

a second electrode layer electrically connected to said first semiconductor layer,

wherein a thickness of said part of said third semiconductor layer between said second region and said second semiconductor layer is made thinner than that of said third semiconductor layer between said first region and said second semiconductor layer.

7. The silicon carbide semiconductor device according to claim 6, wherein said bottom surface of said second region is located to a position deeper than that of said first region.

8. The silicon carbide semiconductor device according to claim 6, wherein said third semiconductor layer has a stepped portion on its surface so that a surface of said third semiconductor is in a particular region for said first region to be formed is made higher than that in a particular region for said second region to be formed.

21. The trench gate type semiconductor device according to claim 6, wherein an entirety of said second region is contained in said third semiconductor layer.

22. The trench gate type semiconductor device according to claim 6, wherein a depth of said bottom surface of said second region is the deepest in said second region.

23. The trench gate type semiconductor device according to claim 6, wherein said second region is provided apart from said second semiconductor layer.

9. A silicon carbide semiconductor device comprising:

a semiconductor substrate made of single crystal silicon carbide, in which a first conductivity type second semiconductor layer and a second conductivity type third semiconductor layer are successively deposited on a first conductivity type first semiconductor layer, said second semiconductor layer having a resistance value higher than said first semiconductor layer;

a first conductivity type semiconductor region formed in a surface portion of said third semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said semiconductor region and said third semiconductor layer and to reach said second semiconductor layer;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

an interlayer insulation film formed on said gate electrode to cover said gate electrode;

a first electrode layer formed on said interlayer insulation layer and electrically connected to said semiconductor region; and

a second electrode layer electrically connected to said first semiconductor layer;

wherein a groove is formed to be distant from said trench in a surface portion of said semiconductor substrate so as to penetrate said semiconductor region and to reach said third semiconductor layer;

said groove has a bottom face contacting said third semiconductor layer; and

said first electrode layer is disposed in said groove apart from said second semiconductor layer.

24. The trench gate type semiconductor device according to claim 9, wherein a part of said third semiconductor layer is disposed between said bottom face of said groove and a top face of said second semiconductor layer.

10. A trench gate type semiconductor device comprising:

a semiconductor substrate in which a second conductivity type second semiconductor layer is deposited on a first conductivity type first semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said second semiconductor layer and to reach said first semiconductor layer;

a first conductivity type semiconductor region formed in a surface portion of said second semiconductor layer, wherein said semiconductor region is disposed around said trench so that a side surface of said semiconductor region is exposed to said trench to define a channel portion in a side surface of said second semiconductor layer exposed to said trench;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

a first electrode layer electrically connected to said semiconductor region;

a second electrode layer electrically connected to said first semiconductor layer; and

a punch-through phenomenon occurring region formed in said second semiconductor layer and electrically connected to said first electrode, wherein a thickness of said second semiconductor layer between said punch-through phenomenon occurring region and said first semiconductor layer is made thinner than that of said second semiconductor layer between said semiconductor region and said first semiconductor layer;

wherein said punch-through phenomenon occurring region is made of first conductivity type semiconductor.

11. The trench gate type semiconductor device according to claim 10, wherein said first semiconductor layer is made up of a low resistance semiconductor layer and a high resistance semiconductor layer, and said second semiconductor layer is disposed on said high resistance semiconductor layer.

12. The trench gate type semiconductor device according to claim 10, wherein said punch-through phenomenon occurring region is made of metal silicide and metal carbide.

13. The trench gate type semiconductor device according to claim 10, wherein a groove is formed in a surface portion of said second semiconductor layer and said first electrode layer filled in said groove serves as said punch-through phenomenon occurring region.

14. The trench gate type semiconductor device according to claim 10, wherein a bottom surface of said punch-through phenomenon occurring region is located to a position deeper than that of said semiconductor region.

15. The trench gate type semiconductor device according to claim 14, wherein said second semiconductor layer has a stepped portion on its surface so that a surface of said second semiconductor layer in a region for said semiconductor region to be formed is made higher than that in a region for said punch-through phenomenon occurring region to be formed.

16. A trench gate type semiconductor device comprising:

a semiconductor substrate in which a second conductivity type second semiconductor layer is deposited on a first conductivity type first semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said second semiconductor layer and to reach said first semiconductor layer;

a first conductivity type semiconductor region formed in a surface portion of said second semiconductor layer, wherein said semiconductor region is disposed around said trench so that a side surface of said semiconductor region is exposed to said trench to define a channel portion in a side surface of said second semiconductor layer exposed to said trench;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

a first electrode layer electrically connected to said semiconductor region; and

a second electrode layer electrically connected to said first semiconductor layer, wherein said trench gate type semiconductor device has a bypass through which current caused by punch-through phenomenon flows between said first electrode layer and said second electrode layer while bypassing an interface of said gate insulation film and said semiconductor region serving as said channel portion;

wherein said bypass is composed of a bypass region that is formed in a surface portion of said second semiconductor layer so that a part of said second semiconductor layer is interposed between a bottom surface of said bypass region and a top surface of said first semiconductor layer in contact with said bottom surface of said bypass region.

17. The trench gate type semiconductor device according to claim 16, wherein a depletion layer extending in a side of said second semiconductor layer does not reach an intersection of said second semiconductor layer, said semiconductor region and said gate insulation file, when voltage is impressed between said first electrode layer and said second electrode layer while no voltage is applied to said gate electrode.

18. The trench gate type semiconductor device according to claim 16, further comprising a connection region which electrically connects said first electrode layer to said semiconductor region, wherein punch-through phenomenon occurs at said connection region when voltage is impressed between said first electrode layer and said second electrode layer while no voltage is applied to said gate electrode.

19. The trench gate type semiconductor device according to claim 18, wherein a thickness of said second semiconductor layer between said semiconductor region and said first semiconductor layer is made thicker than that of said second semiconductor layer between said connection region and said first semiconductor layer.

25. The trench gate type semiconductor device according to claim 16, wherein an entirety of said bypass region is contained in said second semiconductor layer.

26. The trench gate type semiconductor device according to claim 16, said bypass region is made of first conductivity type semiconductor.

27. The trench gate type semiconductor device according to claim 16, wherein said bypass region is provided apart from said first semiconductor layer.

20. A trench gate type semiconductor device comprising:

a semiconductor substrate in which a second conductivity type second semiconductor layer is deposited on a first conductivity type first semiconductor layer;

a trench formed in said semiconductor substrate so as to penetrate said second semiconductor layer and to reach said first semiconductor layer;

a first conductivity type semiconductor region formed in a surface portion of said second semiconductor layer, wherein said semiconductor region is disposed around said trench so that a side surface of said semiconductor region is exposed to said trench to define a channel portion in a side surface of said second semiconductor layer exposed to said trench;

a gate insulation film formed on an inner wall of said trench;

a gate electrode formed on said gate insulation film in said trench;

a first electrode layer electrically connected to said semiconductor region;

a second electrode layer electrically connected to said first semiconductor layer; and

a connection region which electrically connects said first electrode layer to said semiconductor region;

wherein said trench gate type semiconductor device has a bypass through which current caused by punch-through phenomenon flows between said first electrode layer and said second electrode layer while bypassing an interface of said gate insulation film and said semiconductor region serving as said channel portion, the punch-through phenomenon occurs at said connection region when voltage is impressed between said first electrode layer and said second electrode layer while no voltage is applied to said gate electrode, and said connection region is made of first semiconductor type semiconductor.