Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate

• US 6,262,453 B1
• Filed: 04/24/1998
• Issued: 07/17/2001
• Est. Priority Date: 04/24/1998
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/066,033
• Time in Patent Office: 1,180 Days
• Field of Search: 257/341, 257/330, 257/331, 257/335, 257/328, 257/333, 257/334, 257/329, 257/374, 257/395, 257/396, 257/397, 257/304
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

Claims

1. A DMOS power device supported on a substrate of a first conductivity type comprising:

a drain of a first conductivity type disposed at a bottom surface of said substrate;

a gate disposed in a trench opened from a top surface of said substrate, said gate having a polysilicon layer filling said trench padded by a gate-oxide layer;

said gate-oxide layer includes a thick-oxide-layer covering walls of said trench at a lower portion of said trench and a thin-gate-oxide with a thickness thinner than said thick-oxide-layer covering walls of said trench above said lower portion of said trench; and

a buried high-dopant-concentration region of said first conductivity-type disposed at a distance below and away from a bottom of said trench.

2. The DMOS power device of claim 1 further comprising:

a source region of said first conductivity type disposed in said substrate surrounding a top portion of said trench; and

a body region of a second conductivity type disposed in said substrate surrounding said trench and encompassing said source region.

3. The DMOS power device of claim 2 further comprising:

at least a second transistor cell wherein said second transistor cell includes a second gate disposed in a second trench opened from a top surface of said substrate, said second gate having a polysilicon layer filling said second trench padded by a second gate-oxide layer;

said second gate-oxide layer includes a second thick-oxide-layer covering walls of said second trench at a lower portion of said second trench and a second thin-gate-oxide with a thickness thinner than said second thick-oxide-layer covering walls of said second trench above said lower portion of said second trench;

a second buried high-dopant-concentration region of said first conductivity-type disposed at a distance below and away from a bottom of said second trench;

a second source region of said first conductivity type disposed in said substrate surrounding a top portion of said second trench; and

a second body region of a second conductivity type disposed in said substrate surrounding said second trench and encompassing said second source region and said second body region extended to contact said body region of claim 2.

4. The DMOS power device of claim 2 further comprising:

a shallow lightly-doped body-dopant region disposed in said body region surrounding said gate with a region depth greater than said source region.

5. The DMOS power device of claim 4 wherein:

said shallow lightly-doped body region surrounding said gate having a depth ranging from 0.2 to 0.6 micrometers for reducing a device threshold voltage without inducing a punch-through.

6. The DMOS power device of claim 1 wherein:

said thin-gate-oxide layer of said gate-oxide layer having a layer thickness ranging from one-fourth to one-half of a thickness of said thick-gate-oxide layer of said gate-oxide layer.

7. The DMOS power device of claim 1 wherein:

said thick-gate-oxide layer of said gate-oxide layer having a layer thickness ranging from 450 to 4000 Angstroms and said thin-gate-oxide layer of said gate-oxide layer having a layer thickness about one-forth to one-half of said thick-gate-oxide layer ranging from 150 to 1000 Angstroms.

8. The DMOS power device of claim 1 wherein:

said buried high-dopant-concentration region at a distance below and away from said bottom of said trench having a dopant concentration higher than said substrate and lower than said drain region.

9. A trenched power device supported on a substrate comprising:

a gate disposed in a trench filled with a gate layer therein padded by a gate oxide layer comprising a gate oxide-layer of more than one thickness covering side and bottom walls of said trench; and

a buried high-dopant-concentration region disposed at a distance below and away from a bottom of said trench having a same conductivity type as said substrate.

10. The trenched power of claim 9 wherein:

said gate layer is a polysilicon layer.

11. The power device of claim 9 further comprising:

a source region disposed in said substrate surrounding a top portion of said trench having a same conductivity type as said substrate; and

a body region of a different conductivity type than said source region disposed in said substrate surrounding said trench and encompassing said source region.

12. The power device of claim 11 further comprising:

a shallow lightly-doped body-dopant region disposed in said body region surrounding said gate with a region depth greater than said source region.

13. The power device of claim 11 wherein:

said shallow lightly-doped body region surrounding said gate having a depth ranging from 0.2 to 0.6 micrometers for reducing a device threshold voltage without inducing a punch-through.

14. A trenched power device supported on a substrate comprising:

a trenched gate disposed in a trench and a buried high-dopant-concentration region disposed at a distance below and away from a bottom of said trenched gate having a same conductivity type as said substrate.