Level shifting CMOS I/O buffer

• US 6,262,599 B1
• Filed: 04/06/2000
• Issued: 07/17/2001
• Est. Priority Date: 04/06/2000
• Status: Active Grant

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Coughlin, Jr., Terry C., Lawson, William F., Milewski, Joseph M.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/544,132
• Time in Patent Office: 467 Days
• Field of Search: 326/62, 326/68, 326/80, 326/81, 326/83, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.

Claims

1. An output buffer circuit comprising:

an input stage receiving a data signal, wherein the input stage includes a data signal voltage level shifter, and the data signal voltage level shifter outputs a voltage shifted data signal on a data signal path out of the input stage;

a first predrive stage including a first buffer being operatively driven by the voltage shifted data signal and including a second buffer being operatively driven by the voltage shifted data signal;

a second predrive stage comprising a signal combining circuit, said second predrive stage operatively driven by each output of the first and second buffers of the first predrive stage; and

an output driving stage operatively driven by an output of the second predrive stage.

2. The output buffer circuit of claim 1, wherein the data signal received by the input stage has a logic voltage less than or equal to a logic voltage of the output driving stage.

3. The output buffer circuit of claim 1, wherein said first predrive stage further comprises two or more signal voltage level shifters.

4. The output buffer circuit of claim 1, wherein said data signal voltage level shifter includes cross-wired transistors.

5. The output buffer circuit of claim 1, wherein each of the first buffer and the second buffer of said first predrive stage comprises an inverting buffer.

6. The output buffer circuit of claim 1, wherein the voltage shifted data signal is the logical complement of the data signal, and each of the first buffer and the second buffer is an inverting buffer.

7. The output buffer circuit of claim 1, wherein the input stage, the first predrive stage, the second predrive stage, and the output driving stage are implemented using complementary metal oxide semiconductor (CMOS) transistors.

8. The output buffer circuit of claim 1, wherein the signal combining circuit comprises a first logic gate being operatively driven by the first buffer, and a second logic gate being operatively driven by the second buffer.

9. The output buffer circuit of claim 8, wherein said input stage further receives an output-enabling signal, and further comprises an output-enabling signal voltage level shifter, and outputs a level shifted output-enabling signal.

10. The output buffer circuit of claim 1, wherein the output driving stage is adapted to enter a high impedance state when not enabled to drive said data signal out.

11. The output buffer circuit of claim 9, wherein the first logic gate is further operatively driven by one of the level shifted output-enabling signal and the logical complement of the level shifted output-enabling signal, and the second logic gate is further operatively driven by the other one of the level shifted output-enabling signal and the logical complement of the level shifted output-enabling signal.

12. The output buffer circuit of claim 1, wherein an input buffer is operatively coupled to the output node of output driving stage.

13. The output buffer circuit of claim 1, wherein each of the first buffer and the second buffer of the first predrive stage comprises an inverter including:

a first transistor referenced to a first voltage, said first transistor comprising a p-channel field effect transistor (PFET); and

a second transistor referenced to ground, said second transistor comprising an n-channel field effect transistor (NFET).

17. The output buffer circuit of claim 1, wherein each of the voltage level shifter and the first buffer and the second buffer is sized so that the data signal will propagate through the output buffer circuit faster than if the output buffer circuit were operably constructed without the first buffer and the second buffer.

18. The output buffer circuit of claim 8, wherein the first logic gate is a NAND-gate, and the second logic gate is a NOR-gate.

14. An interface circuit for translating a lower-voltage-logic signal into a higher-voltage-logic signal, comprising:

a level-shifter operatively driven by said lower-voltage-logic signal;

two tuning inverters, each of the two tuning inverters being operatively driven by the same output of said level-shifter;

a signal combining circuit operatively driven by an output from each one of said two tuning inverters, said signal combining circuit being adapted to tristate the output of the interface circuit; and

an output driving circuit operatively driven by said signal combining circuit, said output driving circuit being adapted to drive said higher-voltage-logic signal out of the interface circuit.

15. The interface circuit of claim 14, wherein each signal combining circuit is further operatively driven by an output-enable signal.

16. The interface circuit of claim 14, wherein the output driving circuit includes a PFET stacked on an NFET, and wherein each of the two tuning inverters is tuned so that when the output driving circuit is switching, the PFET turns OFF before NFET turns ON.

19. An interface circuit for translating a data signal from a lower-voltage-logic to a higher-voltage-logic, the circuit comprising:

a first voltage level shifter including cross-wired transistors, and the first voltage level shifter being operatively driven by said data signal being received as a lower-voltage-logic signal, the first voltage level shifter outputting a level-shifted complemented data signal, the level-shifted complemented data signal being the logical complement of the data signal level-shifted to the higher-voltage-logic;

a first tuning inverter, being operatively driven by said level-shifted complemented data signal;

a second tuning inverter, being operatively driven by said level-shifted complemented data signal;

a signal combining circuit operatively driven by the output of the first tuning inverter and by the output of the second tuning inverter, said signal combining circuit being adapted to control a tristate output driving circuit of the interface circuit; and

the tristate output driving circuit being adapted to drive the said data signal out of the interface circuit at the higher-voltage-logic.

20. The interface circuit of claim 19, wherein signal combining circuit includes a NAND-gate being operatively driven by the output of the first tuning inverter and further includes a NOR-gate being operatively driven by the output of the second tuning inverter.