Ultrasonic system and method for data transfer, storage and/or processing

• US 6,262,749 B1
• Filed: 12/31/1997
• Issued: 07/17/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Siemens Medical Solutions USA Incorporated (Siemens AG)
• Original Assignee: Acuson Corporation (Siemens AG)
• Inventors: Guracar, Ismayil M., Finger, David J., Fash, D. Grant III, Shakouri, Shahrokh
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/001,268
• Time in Patent Office: 1,294 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/526, 345/507, 345/512, 345/516, 600/437, 600/443, 600/447, 128/915, 128/916, 128/922
• US Class Current: 345/564
• CPC Class Codes: G01S 15/899 Combination of imaging systems with ancillary equipment
• CPC Class Codes: G01S 7/52023 Details of receivers
• CPC Class Codes: G01S 7/52034 Data rate converters
• CPC Class Codes: G01S 7/52057 Cathode ray tube displays
• CPC Class Codes: Y10S 128/916 Ultrasound 3-D imaging

Abstract

An apparatus and method for processing ultrasound data is provided. The apparatus includes an interface operatively connected to a memory, a programmable single instruction multiple data processor (or two symmetric processors), a source of acoustic data (such as a data bus) and a system bus. The memory stores data from the processor, ultrasound data from the source, and data from the system bus. The processor has direct access to the memory. Alternatively, the system bus has direct access to the memory. The interface device translates logically addressed ultrasound data to physically addressed ultrasound data for storage in a memory. The translation is the same for data from both the processor and the source for at least a portion of a range of addresses. The memory stores both ultrasound data and various of: beamformer control data, instruction data for the processor, display text plane information, control plane data, and a table of memory addresses. One peripheral connects to the ultrasound apparatus. An interface adapter, powered from the ultrasound apparatus, translates information transferred between the peripheral and the ultrasound apparatus. The adapter connects non-standard peripherals to various standard interfaces on the ultrasound apparatus.

Claims

1. An ultrasound apparatus for storing data, the apparatus comprising:

an interface device including a logical address translator, an ultrasound image data port, a processor port and a memory port;

a source of ultrasound data comprising data derived from the transmission of acoustic energy, the source operatively connected to the ultrasound image data port;

a processor operatively connected to the processor port;

a memory operatively connected to the memory port; and

a data transfer controller operatively connected to the ultrasound image data port and separate from the interface device;

wherein the interface device translates logical addresses to physical memory addresses the same for ultrasound data from the ultrasound data port and the processor port for at least a portion of a range of addresses and the source comprises at least an ultrasound transducer.

2. The apparatus of claim 1 wherein the interface device comprises a device operable pursuant to an Accelerated Graphics Port specification.

3. The apparatus of claim 1 wherein the interface device comprises a quad port interface device.

4. The apparatus of claim 3 wherein ultrasound image data and a table of physical addresses is stored in the memory.

5. The apparatus of claim 1 wherein:

the processor port comprises a host interface;

the ultrasound image data port comprises an AGP interface; and

the memory comprises a component selected from the group consisting of;

synchronous DRAM and RAMBUS.

6. The apparatus of claim 1 wherein the interface device further comprises a PCI bus interface operatively connected to a system bus.

7. The apparatus of claim 6 wherein the interface device is operable to route data from a first of said ports to a second of said ports with routing data from a third of said ports to a fourth of said ports.

8. The apparatus of claim 6 wherein the interface device translates logical addresses to physical memory addresses the same for ultrasound image data from the ultrasound image data port, the processor port, and the PCI bus interface.

9. The apparatus of claim 1 wherein the interface device is operable to arbitrate between transferring data from first and second of said ports to the memory port.

10. The apparatus of claim 1 wherein the processor comprises a system processor.

11. The apparatus of claim 10 wherein instruction data for the system processor is stored in the memory.

12. The apparatus of claim 1 wherein the processor has direct access to the memory.

13. The apparatus of claim 12 wherein the processor is operable to process ultrasound data and provide control information.

14. The apparatus of claim 1 wherein the ultrasound data port comprises a port operable pursuant to the Accelerated Graphics Port specification;

and

further comprising;

a data transfer controller operatively connected with the ultrasound data port and the ultrasound data source, wherein the ultrasound data source comprises at least two ultrasound data paths; and

at least two ultrasound data destination paths operatively connected with the data transfer controller.

15. A method for storing data in an ultrasound system, the method comprising the steps of:

(a) providing an interface device including a logical address translator, an ultrasound data port, a processor port and a memory port;

(b) translating logical addresses to physical memory addresses for ultrasound data associated with the ultrasound data port;

(c) translating logical addresses to physical memory addresses using a same scheme for ultrasound data associated with the processor port for at least a portion of a range of addresses;

(d) acquiring the ultrasound data responsive to a transmission of acoustic energy; and

(e) controlling a transfer of the ultrasound data associated with the ultrasound data port with a data transfer controller separate from the interface device.

16. The method of claim 15 wherein the step (a) comprises providing a device operable pursuant to an Accelerated Graphics Port (AGP) specification.

17. The method of claim 15 further comprising the step (f) of storing ultrasound image data and a table of physical addresses in the memory.

18. The method of claim 15 wherein the step (a) comprises providing a host interface, an AGP interface, and a interface to a memory, the memory selected from the group consisting of:

synchronous DRAM and RAMBUS.

19. The method of claim 15 wherein the step (a) further comprises providing a PCI bus port operatively connected to a system bus.

20. The method of claim 19 further comprising the step (f) of routing data from a first of said ports to a second of said ports with routing data from a third of said ports to a fourth of said ports.

21. The method of claim 19 further comprising the step (f) of translating logical addresses to physical memory addresses pursuant to the scheme for ultrasound image data associated with the PCI bus port.

22. The method of claim 19 further comprising the step (f) of directly accessing with one bus transaction the memory from any of the ports.

23. The method of claim 15 further comprising the step (f) of arbitrating between transferring data from first and second of said ports to the memory port.

24. The method of claim 15 further comprising the step (f) of directly accessing the memory with a processor operatively connected to the processor port.

25. The method of claim 24 wherein the step (f) comprises accessing instruction data for execution.

26. The method of claim 15 wherein (d) comprises acquiring the ultrasound data with an ultrasonic transducer.

27. The method of claim 15 wherein the ultrasound data port comprises a port operable pursuant to the Accelerated Graphics Port specification;

and

further comprising;

(e) controlling transfer of ultrasound data to the ultrasound data port from one of at least two sources of ultrasound data; and

(f) controlling transfer of ultrasound data from the ultrasound data port to one of at least two destinations for ultrasound data.

28. An ultrasound apparatus for storing data, the apparatus comprising:

an interface device including a logical address translator, an ultrasound image data port, a processor port and a memory port;

a source of ultrasound data comprising data derived from the transmission of acoustic energy, the source operatively connected to the ultrasound image data port;

a processor operatively connected to the processor port;

a memory operatively connected to the memory port;

a data transfer controller operatively connected with the ultrasound data port and the ultrasound data source, the data transfer controller additionally operatively connected with one of an additional source of ultrasound data, a first destination of ultrasound data, a second destination of ultrasound data and combinations thereof,

wherein the interface device translates logical addresses to physical memory addresses the same for ultrasound data from the ultrasound data port and the processor port for at least a portion of a range of addresses and the source comprises at least an ultrasound transducer.

29. The apparatus of claim 28 wherein the ultrasound data port comprises a port operable pursuant to the Accelerated Graphics Port specification, wherein the ultrasound data source comprises at least two ultrasound data paths, and wherein at least two ultrasound data destination paths operatively connect with the data transfer controller.

30. The apparatus of claim 28 wherein the data transfer controller is separate from the interface device;

and

wherein the processor, the system bus and the data transfer controller have direct access to the memory.

31. The apparatus of claim 28 wherein the interface device comprises a quad port interface device.

32. The apparatus of claim 28 wherein:

the processor port comprises a host interface;

the ultrasound image data port comprises an AGP interface;

the memory comprises a component selected from the group consisting of;

synchronous DRAM and RAMBUS; and

a PCI bus interface operatively connects to a system bus.

33. The apparatus of claim 28 wherein the processor comprises a system processor and wherein instruction data for the system processor is stored in the memory, and wherein the processor is operable to process ultrasound data.

34. A method for storing data in an ultrasound system, the method comprising the steps of:

(a) providing an interface device including a logical address translator, an ultrasound data port, a processor port and a memory port;

(b) translating logical addresses to physical memory addresses for ultrasound data associated with the ultrasound data port;

(c) translating logical addresses to physical memory addresses using a same scheme for ultrasound data associated with the processor port for at least a portion of a range of addresses;

(d) acquiring the ultrasound data responsive to a transmission of acoustic energy;

(e) controlling transfer of ultrasound data to the ultrasound data port from a first source of ultrasound data; and

(f) additionally controlling transfer of ultrasound data from the ultrasound data port to one of a second source of ultrasound data, a first destination of ultrasound data, a second destination of ultrasound data and combinations thereof.

35. The method of claim 34 wherein (d) comprises acquiring the ultrasound data with an ultrasonic transducer.

36. The method of claim 34 wherein the ultrasound data port comprises a port operable pursuant to the Accelerated Graphics Port specification;

and

(e) comprises controlling transfer of ultrasound data to the ultrasound data port from one of at least two sources of ultrasound data; and

(f) comprises controlling transfer of ultrasound data from the ultrasound data port to one of at least two destinations for ultrasound data.

37. The method of claim 34 wherein (e) and (f) comprise controlling transfer of ultrasound data associated with the ultrasound data port with a data transfer controller separate from the interface device.

38. The method of claim 34 wherein the step (a) comprises providing a host interface, an AGP interface, and a interface to a memory, the memory selected from the group consisting of:

synchronous DRAM and RAMBUS and further comprises providing a PCI bus port operatively connected to a system bus.

39. The method of claim 34 further comprising:

(g) providing control information through the processor port and accessing ultrasound data through the processor port.