Semiconductor memory device having a ferroelectric memory capacitor

• US 6,262,910 B1
• Filed: 10/13/1999
• Issued: 07/17/2001
• Est. Priority Date: 10/13/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maeda, Kengo, Takata, Hidekazu
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/417,274
• Time in Patent Office: 643 Days
• Field of Search: 368/145, 368/149, 368/230.06, 368/117, 368/203, 368/189.01
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.

Claims

1. A semiconductor memory device comprising:

a plurality of bit lines disposed on a substrate;

a plurality of word lines disposed on the substrate;

a plurality of plate lines disposed on the substrate;

a memory cell array including a plurality of memory cells arranged in a matrix having a plurality of columns and rows;

each of the memory cells including at least one MOS transistor and at least one memory capacitor;

the memory capacitor including a first capacitor electrode, a second capacitor electrode and a ferroelectric film;

the MOS transistor including a gate, a first transistor electrode and a second transistor electrode;

the gate of each MOS transistor in a same column being connected to a same word line;

each of the MOS transistors in a same row being connected to a same bit line at the first transistor electrode;

the second transistor electrode being connected to the memory capacitor at the first capacitor electrode;

the plate line being connected to the second capacitor electrode so that a plurality of memory capacitors are selected in the plate line in the column direction or in the row direction;

a gate voltage supply section for supplying, at a time of power on, a predetermined voltage to the gates of the MOS transistors connected to the word line to activate the MOS transistors and to connect the bit line and the first capacitor electrode so that the bit line and the first capacitor electrode have the same potential via the MOS transistor; and

a potential control section which makes the potential of the bit line and the plate line the same so that the first capacitor electrode and the second capacitor electrode have the same potential.

3. A semiconductor memory device according to claim 1 or 2, wherein the potential control section includes a switching transistor for controlling the conduction of current;

and

by supplying a predetermined voltage to the gate of the switching transistor to activate the switching transistor, the bit line and the plate line are connected so that the bit line and the plate line have the same potential.

4. A semiconductor memory device according to claim 3, wherein the gate voltage supply section includes a power on reset circuit for supplying a predetermined output voltage to at least one word line connected to the gate of the MOS transistor, at the time of power on, or for a predetermined period of time since returning from a power down mode, to activate the MOS transistor to thereby connect the bit line and the first capacitor electrode;

the power on reset circuit further supplying a predetermined output voltage to the gate of the switching transistor to activate the switching transistor to thereby make the potential of the first capacitor electrode and the second capacitor electrode the same.

5. A semiconductor memory device according to claim 4, wherein the power on reset circuit further includes a boosting circuit for boosting the output voltage up to a power supply voltage or higher.

6. The semiconductor memory device according to claim 3, wherein the potential control section includes:

a voltage supply circuit for supplying a predetermined voltage.

7. The semiconductor memory device according to claim 6, wherein the voltage supply circuit supplies a predetermined voltage to the bit line via the switching transistor.

8. The semiconductor memory device according to claim 6, wherein the voltage supply circuit supplies a predetermined voltage to the plate line via the switching transistor.

9. The semiconductor memory device according to claim 6, wherein the voltage supply circuit supplies a predetermined voltage to the plate line and bit line via the switching transistor.

10. The semiconductor memory device according to claim 6, wherein the voltage supply circuit supplies a predetermined voltage to the bit line and the plate line based on a power on detection signal sent out at the time of power on or at the time of returning from the power down mode.

11. The semiconductor memory device according to claim 6, wherein the potential control section further includes at least a second switching transistor for supplying a voltage from the voltage supply circuit to the bit line.

12. The semiconductor memory device according to claim 11, wherein the voltage supply circuit further supplies a predetermined voltage to the plate line so that the plate line and bit line are at the same potential.

13. The semiconductor memory device according to claim 6, wherein the potential control section further includes at least a second switching transistor for supplying a voltage from the voltage supply circuit to the plate line.

14. The semiconductor memory device according to claim 13, wherein the voltage supply circuit further supplies a predetermined voltage to the bit line so that the plate line and bit line are at the same potential.

15. A semiconductor memory device according to claim 1 or 2, wherein the potential control section includes:

a voltage supply circuit for supplying a predetermined voltage; and

a switching transistor for supplying a voltage from the voltage supply circuit to the bit line;

wherein a predetermined voltage is supplied to a gate of the switching transistor to activate the switching transistor so that the bit line and the plate line have the same potential.

16. A semiconductor memory device according to claim 15, wherein the voltage supply circuit further supplies a predetermined voltage to the plate line so that the bit line and the plate line have the same potential.

17. A semiconductor memory device according to claim 15, wherein the switching transistor further supplies a voltage from the voltage supply circuit to the plate line.

18. A semiconductor memory device according to claim 15, wherein the gate voltage supply section includes a power on reset circuit for supplying a predetermined output voltage to at least one word line connected to the gate of the MOS transistor, at the time of power on, or for a predetermined period of time since returning from the power down mode, to activate the MOS transistor to thereby connect the bit line and the first capacitor electrode;

the power on reset circuit further supplying a predetermined output voltage to the gate of the switching transistor to activate the switching transistor to thereby make the potential of the first capacitor electrode and the second capacitor electrode the same.

19. A semiconductor memory device according to claim 15, wherein the power on reset circuit further includes a boosting circuit for boosting the output voltage up to a power supply voltage or higher.

20. A semiconductor memory device according to claim 1 or 2, wherein the potential control section includes:

a voltage supply circuit for supplying a predetermined voltage; and

a switching transistor for supplying a voltage from the voltage supply circuit to the plate line;

wherein a predetermined voltage is supplied to a gate of the switching transistor to activate the switching transistor so that the bit line and the plate line have the same potential.

21. A semiconductor memory device according to claim 20, wherein the gate voltage supply section includes a power on reset circuit for supplying a predetermined output voltage to at least one word line connected to the gate of the MOS transistor, at the time of power on, or for a predetermined period of time since returning from the power down mode, to activate the MOS transistor to thereby connect the bit line and the first capacitor electrode;

the power on reset circuit further supplying a predetermined output voltage to the gate of the switching transistor to activate the switching transistor to thereby make the potential of the first capacitor electrode and the second capacitor electrode the same.

22. A semiconductor memory device according to claim 21, wherein the power on reset circuit further includes a boosting circuit for boosting the output voltage up to a power supply voltage or higher.

23. A semiconductor memory device according to claim 1 or 2, wherein the potential control section includes a voltage supply circuit for supplying a predetermined voltage to the bit line and the plate line.

24. A semiconductor memory device according to claim 23, wherein the voltage supply circuit supplies a predetermined voltage to the bit line and plate line based on a power on detection signal sent out at the time of power on or at the time of returning from the power down mode, to thereby make the potential of both of the bit line and the plate line the same.

25. A semiconductor memory device according to claim 23 further including a first switching transistor for supplying a predetermined voltage to the bit line from the voltage supply circuit;

and a second switching transistor for supplying a predetermined voltage to the plate line from the voltage supply circuit;

a predetermined voltage being supplied to the first and second switching transistors to thereby make the potential of both of the bit line and the plate line the same.

26. A semiconductor memory device according to claim 23, wherein the gate voltage supply section includes a power on reset circuit for supplying a predetermined output voltage to at least one word line connected to the gate of the MOS transistor, at the time of power on, or for a predetermined period of time since returning from the power down mode, to activate the MOS transistor to thereby connect the bit line and the first capacitor electrode;

the power on reset circuit further supplying a power on detection signal to the voltage supply circuit to supply predetermined voltage to the bit line and the plate line so that the potential of both lines becomes the same.

27. A semiconductor memory device according to claim 26, wherein the power on reset circuit further includes a boosting circuit for boosting the output voltage up to a power supply voltage or higher.

2. A semiconductor memory device comprising:

a plurality of bit lines disposed on a substrate;

a plurality of word lines disposed on the substrate;

a plurality of plate lines disposed on the substrate;

a memory cell array including a plurality of memory cells arranged in a matrix having a plurality of columns and rows;

each of the memory cells including at least one MOS transistor and at least one memory capacitor;

the memory capacitor including a first capacitor electrode, a second capacitor electrode and a ferroelectric film;

the MOS transistor including a gate, a first transistor electrode and a second transistor electrode;

the gate of each MOS transistor in a same column being connected to a same word line;

each of the MOS transistors in a same row being connected to a same bit line at the first transistor electrode;

the second transistor electrode being connected to the memory capacitor at the first capacitor electrode;

the plate line being connected to the second capacitor electrode so that a plurality of memory capacitors are selected in the plate line in the column direction or in the row direction;

a gate voltage supply section for supplying a predetermined voltage to the gates of the MOS transistors connected to the word line to activate the MOS transistors and to connect the bit line and the first capacitor electrode via the MOS transistor so that the bit line and the first capacitor electrode have the same potential after power on and when the plate line or the bit line, supplied with a predetermined voltage, is returned from a power down mode for reducing the electric power consumption to an optional predetermined potential, regardless of being at a time of operation or in a standby state; and

a potential control section for making the potential of the bit line and the plate line the same so that the first capacitor electrode and the second capacitor electrode have the same potential.