Hardware and software co-simulation including simulating the cache of a target processor

• US 6,263,302 B1
• Filed: 01/26/2000
• Issued: 07/17/2001
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: VaST Systems Technology Corp. (Synopsys Incorporated)
• Inventors: Torossian, James R., Hellestrand, Graham R., Chan, Ricky L. K., Kam, Ming Chi, Cheung, King Yin, Yong, Foo Ngok
• Primary Examiner(s): Teska, Kevin
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US09/491,390
• Time in Patent Office: 538 Days
• Field of Search: 703/13, 703/17, 703/19, 703/6, 703/28, 703/14, 703/22, 703/27, 716/3, 716/18
• US Class Current: 703/17
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 8/30 Creation or generation of source code
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.

Claims

1. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a cache, and an accompanying user program to be executed on the target processor, the design system comprising:

a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,

wherein the processor simulator includes

a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry,

a cache simulator for simulating the operation of the cache;

wherein determining the analyzed version of the user program includes;

decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing, and

identifying those parts of the user program that include one or more references that might require a cache lookup;

such that executing the analyzed version of the user program;

(i) causes the cache simulator to be invoked for at least one of the references that includes a memory reference that requires a cache lookup, invoking the cache simulator accounting for the effect of any cache misses on timing, and

(ii) produces accurate timing information incorporating target processor instruction timing and cache effects.

2. The design system of claim 1,

wherein the target processor includes a pipeline, and wherein the time calculating incorporates pipeline effects, such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing, cache effects, and pipeline effects.

3. The design system of claim 1, wherein executing the analyzed version of the user program causes the cache simulator to be invoked for any reference that include a memory reference that requires a cache lookup.

4. The design system of claim 3,

wherein the user program includes statements in a high level language,

wherein decomposing the user program into linear blocks includes parsing the user program to determine linear block boundaries,

wherein calculating the time delay for each linear block comprises:

cross-compiling the user program to produce target code;

parsing the cross-compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program, the time delay determining using characteristics of the target processor; and

calculating the time delay for each linear block of the user program from the time delays determined in the target code parsing step, and

wherein identifying those parts of the user program that include one or more references that might require a cache lookup further includes;

inserting hooks in the user program to invoke, at run time, the cache simulator for any reference that includes a memory reference.

5. The design system of claim 4,

wherein the processor simulator further includes a memory mapper that translates between host memory addresses and target memory addresses, the translation using memory mapping information, and

wherein invoking the cache simulator for one of the memory references further includes invoking the memory mapper to translate the host memory address for the memory reference into the target memory address for the memory reference.

6. The design system of claim 5,

wherein the target digital circuitry including one or more devices coupled to the target processor, each device having a target address,

wherein the memory mapper also translates between the host addresses of each of the devices and the target addresses of each of the devices,

wherein the identifying step of determining the analyzed version of the user program includes identifying those parts of the user program that include one or more references that each is either a memory references or a reference that require a read or write to a device, and inserting hooks in the user program to invoke, at run time, a reference process for each of the references, the reference process including:

determining if the reference is a memory reference or a device reference, and if a device reference, determining the target address of the device, and causing the processor simulator to communicate with the hardware simulator via the communication mechanism to cause the device to be written to or read from, and if a memory reference, invoking the cache simulator for the memory reference.

7. The design system of claim 4,

wherein the processor simulator further includes a memory allocation simulator that allocates memory on the host computer system while simulating the allocation of memory by the target processor, and

wherein the analysis process includes inserting hooks in the user program to invoke the memory allocation simulator during execution of the analyzed program that correspond to dynamic memory allocations that would occur if the user program was being executed on the target processor.

8. The design system of claim 3,

wherein the cache includes a data-cache and the processor simulator includes a data cache model, and

wherein identifying those parts of the user program that include one or more references that might require a cache lookup further includes:

identifying those parts of the user program that include one or more memory references that require a data-cache lookup, and

inserting hooks in the user program to invoke, at run time, the cache simulator using the data-cache model for the memory references that require a data-cache lookup.

9. The design system of claim 3,

wherein the cache includes an instruction-cache and the processor simulator includes an instruction-cache model, and

wherein identifying those parts of the user program that include one or more memory references that might require a cache lookup further includes:

identifying those parts of the user program that include one or more memory references that require an instruction-cache lookup, and

inserting hooks in the user program to invoke, at run time, the cache simulator using the instruction cache model for the memory references that require an instruction cache lookup.

10. The design system of claim 4, wherein the analyzed user program includes instructions for accumulating the calculated linear block time delays, and executing the analyzed program includes executing the user program and executing the time delay accumulation instructions.

11. The design system of claim 4, wherein executing the analyzed program includes executing the user program while making reference to the calculated linear block time delays.

12. The design system of claim 3,

wherein the processor simulator and the hardware simulator process independently of each other.

13. The design system of claim 3,

wherein the processor simulator communication mechanism communicates information associated with the event to the hardware simulator, and

wherein the hardware simulator receives the associated event information.

14. The design system of claim 13,

wherein the hardware simulator processes the associated event information.

15. The design system of claim 14,

wherein the event information includes time delay information indicating an amount of simulated time since a previous event, and

wherein, upon receiving the time delay information, the hardware simulator executes an appropriate amount of hardware simulation time.

16. The design system of claim 3,

wherein the host computer system includes a computer network containing a first and a second host computer,

wherein the processor simulator operates on the first host computer,

wherein the hardware simulator operates on the second host computer, and

wherein the processor simulator is coupled to the hardware simulator by a computer network connection of the computer network, and

wherein the interface mechanism controls communications over the network connection.

17. The design system of claim 14, further comprising

a suspend mechanism coupled to the processor simulator that temporarily halts execution of the user program on the processor simulator while the hardware simulator processes the event information.

18. The design system of claim 17, wherein the interface mechanism includes the suspend mechanism.

19. The design system of claim 14,

wherein the hardware simulator processing the event information produces an event result, and,

wherein the hardware simulator includes a mechanism to communicate the event result to the processor simulator using the interface mechanism.

20. The design system of claim 19, wherein the event result is an interrupt, and is processed upon receipt of the event result by the processor simulator.

21. The design system of claim 19, further including

a resumption mechanism coupled to the processor simulator to resume execution of the user program upon receipt of the event result.

22. The design system of claim 4, wherein the cache simulator returns a time delay when the cache simulator determines there is a cache miss.

23. The design system of any of claims 4-22, wherein the significant event is the cache simulator determining that there is a cache miss that requires a number of bus cycles to be executed, the number of bus cycles determined by characteristics of the cache.

24. The design system of claim 23, further comprising

a suspend mechanism coupled to the processor simulator,

wherein the target processor includes a bus and wherein the target digital circuitry simulated by the hardware simulator includes a bus model,

wherein the processor simulator communication mechanism communicates information associated with the event to the hardware simulator,

wherein the hardware simulator receives the associated event information and processes the associated event information, processing the associated event information including processing the number of bus cycles, and

wherein the suspend mechanism temporarily halts execution of the user program on the processor simulator while the hardware simulator processes the event information.

25. The design system of claim 3, wherein the event requiring the user program to interact with the target digital circuitry is an input/output instruction to the hardware simulator.

26. The design system of claim 3, wherein the processor simulator uses a first data format and the hardware simulator uses a second data format, the system further including a translator to convert the associated event information from the first data format to the second data format.

27. The design system of claim 19,

wherein the hardware simulator contains a processor model shell to access of at least some of the external hardware signals of the target processor connected to the digital circuitry in the electronic system, and

wherein the processor simulator uses a first data format and the hardware simulator uses a second data format,

the design system further including a mapper to map an event result in the second data format to the first data format.

28. The design system of claim 27, wherein the host computer system includes a computer network, wherein the processor simulator is coupled to the translator and the mapper by a first computer network connection of the computer network, the interface mechanism controlling communication between the processor simulator, and the translator and the mapper over the first network connection.

29. The design system of claim 28, wherein the translator and the mapper are coupled to the hardware simulator by a second computer network connection of the computer network, the interface mechanism controlling communication between the translator and the mapper, and the hardware simulator over the first and second network connections.

30. The design system of claim 3, wherein the hardware simulator operates in a hardware description language, and at least some of the digital circuitry is specified in the hardware description language.

31. The design system of claim 3, wherein the hardware simulator provides for modeling digital circuitry in a high level language and, wherein at least some of the digital circuitry is specified in the high level language.

32. The design system of claim 3, wherein the interface mechanism includes a message passing kernel.

33. The design system of claim 32, wherein the processor simulator and the hardware simulators are tasks under the kernel.

34. The design system of claim 32, wherein the host computer system includes a plurality of host processors, and, wherein the processor simulator and the hardware simulators execute on different host processors.

35. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, first and second target processors, and accompanying first and second user programs to be executed on each of the target processors, at least the first target processor having a cache, the design system comprising:

a first processor simulator using software executing on the host computer system for simulating execution of the first user program on the first target processor, the software including an analyzed version of the first user program;

a second processor simulator using software executing on the host computer system for simulating execution of the second user program on the second target processor, the software including an analyzed version of the second user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the first and second processor simulators, including controlling communication between the first and second processor simulators and the hardware simulator,

wherein the first processor simulator includes a first mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the first user program with the target digital circuitry,

wherein the second processor simulator includes a second mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the second user program with the target digital circuitry,

wherein determining the analyzed version of each user program includes decomposing the respective user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the respective target processor, the time calculating incorporating respective target processor'"'"'s instruction timing,

wherein determining the analyzed version of the first user program further includes identifying those parts of the first user program that include one or more references that might require a cache lookup,

such that executing the analyzed version of each user program produces accurate timing information incorporating the respective target processor instruction timing including any cache effects in the case of the first target processor.

36. The design system of claim 35, wherein at least one of the target processors includes a pipeline, and wherein the time calculating for determining the analyzed version of the user program for the target processor that includes the pipeline also incorporates pipeline effects, such that executing the analyzed version of the user program for the target processor that includes the pipeline produces timing information that also incorporates pipeline effects.

37. The design system of claim 35, wherein the first and second processor simulators and the hardware simulator process independently of each other.

38. The design system of claim 35,

wherein the first processor simulator communication mechanism communicates information associated with the first user program event to the hardware simulator,

wherein the second processor simulator communication mechanism communicates information associated with the second user program event to the hardware simulator,

wherein the hardware simulator receives the first user program associated event information, and

wherein the hardware simulator receives the second user program associated event information.

39. The design system of claim 38,

wherein the hardware simulator processes the first user information associated event information, generating a first user program event result, and

wherein the hardware simulator processes the second user information associated event information, generating a second user program event result.

40. The design system of claim 39,

wherein each event information includes time delay information indicating an amount of simulated time since the hardware simulator last received previous event information from the respective user program, and

wherein, upon receiving the time delay information from either of the processor simulators, the hardware simulator executes an appropriate amount of hardware simulation time.

41. The design system of claim 40, wherein the time delay information is forwarded to the hardware simulator from either of the processor simulator when no event information has been conveyed by that processor simulator to the hardware simulator within a predetermined amount of time.

42. The design system of claim 35,

wherein the host computer system includes a computer network containing a first and a second host computer,

wherein the processor simulator operates on the first host computer, wherein the hardware simulator operates on the second host computer,

wherein the processor simulator is coupled to the hardware simulator by a computer network connection of the computer network, and

wherein the interface mechanism controls communications over the network connection.

43. The design system of claim 35, further comprising:

first and second suspend mechanisms respectively coupled to the first and second processor simulators, each suspend mechanism temporarily halting execution of the respective user program on the respective processor simulator while the hardware simulator processes the respective user program event information.

44. The design system of claim 43,

wherein the interface mechanism includes the suspend mechanisms.

45. The design system of claim 39, wherein the hardware simulator processes the event information producing an event result for information associated with each event, and

wherein the hardware simulator includes a mechanism to communicate the event result to the respective processor simulator whose user program produced the event, using the interface mechanism.

46. The design system of claim 45, wherein one of the event results is an interrupt for a particular target processor, and is processed upon receipt of the event result by one of the processor simulator associated to the event.

47. The design system of claim 45 further including first and second resumption mechanisms respectively coupled to the first and second processor simulators to resume execution of the respective user program upon receipt of the respective user program event result.

48. The design system of claim 35,

wherein the host computer system includes a computer network, and,

wherein the first and second processor simulators are each coupled to the hardware simulator by a respective computer network connection of the computer network, the interface mechanism controlling communications over the network connections.

49. The design system of claim 35,

wherein the one of the user program events is an input/output instruction to the hardware simulator, and

wherein the interface mechanism controls communication of the input/output instruction from the event-associated processor simulator to the hardware simulator.

50. The design system of claim 35,

wherein the first and second processor simulators use a first data format and the hardware simulator uses a second data format, the system further including a translator to convert the events when the first or second user program for the first or second target processor, respectively, requires interaction with the target digital circuitry from the first data format to the second data format.

51. The design system of claim 50, wherein the hardware simulator contains first and second processor model shells to simulate activation of the pins of the first and second target processors, respectively, the system further including a mapper to map an event result in the second data format to the first processor data format.

52. The design system of claim 35, wherein the interface mechanism includes a message passing kernel.

53. A method of simulating an electronic system that includes target digital circuitry and a target processor having a cache, the method comprising:

(a) simulating execution of the user program on the target processor by executing the analyzed version of the user program on the host processor, the executing of the analyzed version including invoking a cache simulation process for a memory reference in the user program, and accumulating accurate timing information, the cache simulation process simulating the cache to account for the timing effects of a cache miss, and the accurate timing information including incorporating instruction timing;

(b) simulating the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating accurate timing information; and

(c) passing communication between the simulation of execution of the user program and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry.

54. The method according to claim 53, wherein the analyzed version of the user program is obtained by an analysis process including:

decomposing the user program into linear blocks, calculating the time delay related to the delay that would be incurred by executing each linear block on the target processor with no cache misses, identifying those parts of the user program that have one or more references that might require a cache lookup, and inserting hooks into the user program to invoke the cache simulation process for the one or more memory references, the time delay calculating incorporating target processor instruction timing according to the target processor characteristics.

55. The method according to claim 54, wherein the target processor includes a pipeline, and wherein the time calculating incorporates pipeline effects, such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing, cache effects, and pipeline effects.

56. The method according to claim 53, wherein one of the significant events is a particular event requiring the user program to interact with the hardware simulator, and wherein the communication is information associated with the particular event, the associated event passed to the hardware simulator.

57. The method according to claim 56, further comprising:

(d) receiving and processing the associated event information at the processor simulator.

58. The method according to claim 57, wherein the associated event information includes time delay information indicating an amount of simulated time since a previous significant event, and wherein said step (d) of processing executes an appropriate amount of hardware simulation time.

59. The method according to claim 58, further comprising:

(e) suspending step (a) of simulating execution of the user program while the associated event information is processed in said step (d).

60. The method according to claim 58, wherein said associated event processing step (d) produces an event result.

61. The method according to claim 59, wherein said associated event processing step (d) produces an event result, the method further including:

(f) resuming said execution user program simulating step (a) when the event result is produced.

62. The method according to claim 61, wherein the event result is an asynchronous event, and wherein said resuming step (b) causes simulation of execution of an asynchronous event handler, the handler being part of the user program.

63. The method according to claim 62, wherein the asynchronous event occurs before the processor simulator executes the appropriate amount of hardware simulation time.

64. The method according to claim 54, further including:

(d) modeling one or more aspects of the target processor execution at a user selected level of detail.

65. The method according to claim 64, wherein the analyzing step further comprises:

inserting hooks into the user program that causes at run time the one or more aspects of the target processor execution to be simulated at the selected level of accuracy.

66. The method according to claim 64, wherein the one or more aspects are modeled in hardware, and wherein the inserted code causes the one or more aspects to be simulated on the hardware simulator.

67. A method for creating a processor model for simulating the operation of a target processor executing a user program, the processor model for use in a simulation design system operable on a host computer system to simulate an electronic system that contains target digital circuitry and the target processor, the target processor having a cache, the design system including a hardware simulator for simulating the digital circuitry on the host computer system, the method comprising:

(a) creating a processor model shell for operation on the hardware simulator, the processor model shell accessing one or more signals of the target processor accessible to digital circuitry external to the target processor;

(b) creating a software shell to provide the user program access to the processor signals coupled to the digital circuitry in the electronic system; and

(c) creating target processor specific information for use in analyzing a user program to determine user program timing information such that when the user program is run on a processor simulator operating on the host computer system, the processor simulator accurately simulates execution, including providing timing, as if the user program was executing on the target processor, the timing taking into account instruction timing and pipeline effects,

the user program analyzing including;

decomposing the user program into linear blocks, calculating the time delay related to the delay that would be incurred by executing each linear block on the target processor with no cache misses, identifying those parts of the user program that have one or more references that might require a cache lookup, and inserting hooks into the user program to invoke the cache simulation process for any references that include a memory reference that requires a cache lookup, the time delay calculating using the target processor specific information.

68. The method of claim 67,

wherein the hardware simulator simulates hardware described in a hardware description language, and

wherein the processor model shell comprises an interface in the hardware description language.

69. The method of claim 68, wherein the software shell comprises high-level computer language code.

70. The method of claim 67,

wherein the hardware simulator simulates hardware using a high level language, and

wherein the processor model shell comprises an interface in the high level language.

71. The method of claim 67,

wherein the user program includes high level computer language code,

wherein determining the time delay for each linear block comprises:

cross-compiling the user program to produce target code;

parsing the cross-compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program; and

determining the time delay for each linear block of the user program from the time delays determined in the target code parsing step, and

wherein the target processor specific information includes information on how to parse cross-compiled target code.

72. The method of claim 67,

wherein the hardware simulator defines the simulation time frame, and

wherein the software shell further provides a user program access to the hardware simulator for the purpose of user program time control.

73. The method of claim 67, further including:

selecting a level of detail of the processor model.

74. The method of claim 73, wherein said selecting a level of detail further includes:

modeling in hardware one or more aspects of the target processor execution where greater accuracy is desired, execution of the one or more aspects simulated on the hardware simulator.

75. The method of claim 73, wherein the user program analyzing further includes inserting code into the user program that simulates at execution time one or more aspects of the target processor execution where greater accuracy is desired.

76. The method of claim 75, wherein inserted code includes code that causes the hardware simulator to simulate at least part of the one or more aspects of the target processor execution.

77. A method of simulating on a host computer system the execution of a user program on a target processor having a cache, the method comprising:

(a) decomposing the user program into linear blocks;

(b) determining linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor with no cache misses, the determining using characteristics of the target processor including instruction timing and cache characteristics, the block timing information taking into account instruction timing and pipeline effects; and

(c) identifying those parts of the user program that include one or more references that might require a cache lookup;

(d) inserting hooks into the user program to invoke a cache simulation process for any reference that includes a memory reference requiring a cache lookup;

(e) combining the linear block timing information with the user program;

(f) executing the combined user program and linear block timing information on the host computer system; and

(g) simulating the target digital circuitry on a hardware simulator running on the host computer system,

wherein execution of the combined user program and linear block timing information on the host computer system includes communicating with the hardware simulator when an event requires interaction of the user program with the target digital circuitry,

such that the execution of the combined user program and linear block timing information on the host computer system simulates the execution of the user program on the target processor including providing accurate execution timing that takes into account instruction timing and cache effects.

78. The method of claim 77,

wherein the user program includes statements in a high level language,

wherein the step of decomposing the user program into linear blocks includes parsing the user program to determine linear block boundaries,

wherein determining the time delay for each linear block comprises:

cross-compiling the user program to produce target code;

parsing the cross-compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program, the time delay determining using characteristics of the target processor; and

determining the time delay for each linear block of the user program from the time delays determined in the target code parsing step.

79. The method of claim 78,

wherein combining the linear block timing information with the user program produces an analyzed user program that includes instructions for accumulating the timing delay, and

wherein the executing executes the analyzed user program on the host processor.

80. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor having a target processor bus, the design system comprising:

a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,

wherein the processor simulator includes

a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry,

wherein at least some of the operation of the target processor bus may be simulated by running a hardware model of the target processor bus on the hardware simulator,

wherein determining the analyzed version of the user program includes;

decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing,

such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

81. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the target digital circuitry including target memory for the target processor, the design system comprising:

a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,

wherein the processor simulator includes

a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and

a memory mapper that translates between host memory addresses and target memory addresses, the translation using memory mapping information,

wherein at least some of the operation of the target memory may be simulated by running a hardware model of the target memory on the hardware simulator,

wherein the contents of the simulated target memory are stored on the host computer system,

wherein determining the analyzed version of the user program includes;

decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing,

such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

82. The design system of claim 81,

wherein the user program includes statements in a high level language,

wherein decomposing the user program into linear blocks includes parsing the user program to determine linear block boundaries,

wherein calculating the time delay for each linear block comprises:

cross-compiling the user program to produce target code;

parsing the cross-compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program, the time delay determining using characteristics of the target processor; and

calculating the time delay for each linear block of the user program from the time delays determined in the target code parsing step.

83. The design system of claim 82,

wherein the processor simulator further includes a memory allocation simulator that allocates memory on the host computer system while simulating the allocation of memory by the target processor, and

wherein the analysis process includes inserting hooks in the user program to invoke the memory allocation simulator during execution of the analyzed program that correspond to dynamic memory allocations that would occur if the user program was being executed on the target processor.

84. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the design system comprising:

a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,

wherein the processor simulator includes

a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and

a memory allocation simulator that allocates memory on the host computer system while simulating the allocation of memory by the target processor,

wherein determining the analyzed version of the user program includes;

decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing, and

inserting hooks in the user program to invoke the memory allocation simulator during execution of the analyzed program that correspond to dynamic memory allocations that would occur if the user program was being executed on the target processor, and

such that executing the analyzed version of the user program produces accurate timing information incorporating target processor instruction timing.

85. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor, and an accompanying user program to be executed on the target processor, the target digital circuitry including one or more devices coupled to the target processor, each device having a target address, the design system comprising:

a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;

a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and

an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,

wherein the processor simulator includes

a communication mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, and

wherein determining the analyzed version of the user program includes;

decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing, and

identifying those parts of the user program that include one or more references that might require a read or write to a device;

such that executing the analyzed version of the user program

(i) causes the processor simulator to communicate with the hardware simulator via the communication mechanism to cause the device to be written to or read from for any reference that is a device reference requiring a read or write to a device, and

(ii) produces accurate timing information incorporating target processor instruction timing.

86. The design system of claim 85,

wherein the processor simulator further includes a memory mapper that translates between the host addresses of each of the devices and target addresses of each of the devices, and

wherein the analysis process includes inserting hooks in the user program to invoke during execution of the analyzed program a reference process for each of the references, the reference process including: determining if the reference is a memory reference or a device reference, and if a device reference, determining the target address of the device, and causing the processor simulator to communicate with the hardware simulator via the communication mechanism to cause the device to be written to or read from.