Method and apparatus for converting between different digital data representation formats

• US 6,263,353 B1
• Filed: 02/17/1999
• Issued: 07/17/2001
• Est. Priority Date: 02/17/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Borgeson, Brian L., Gross, Danny B., OʼDonnell, Michael D.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/251,495
• Time in Patent Office: 881 Days
• Field of Search: 708/204, 341/55, 711/220
• US Class Current: 708/204
• CPC Class Codes: G06F 7/768 Data position reversal, e.g. bit reversal, byte swapping

Abstract

A method and apparatus for converting digital data representations, such as network addresses of different computer networks. Input data, which in one embodiment includes a hexadecimal network address, contains a plurality of bytes, with each byte having a plurality of digits arranged in positions. A first set of digits from the bytes is selected having a first digit position. The digits in the first set are shifted to a second digit position to generate a first resultant. A second set of digits is selected having a third digit position. The digits in the second set are shifted to a fourth digit position to generate a second resultant. The first and second resultants are summed to generate a converted output network address.

Claims

1. A method for converting digital data representations, comprising:

receiving input data, the input data including a plurality of bytes, each byte having a plurality of digits arranged in positions;

selecting a first set of digits from the bytes having a first digit position;

shifting the digits in the first set of digits to a second digit position to generate a first resultant;

selecting a second set of digits from the bytes having a third digit position;

shifting the digits in the second set of digits to a fourth digit position to generate a second resultant; and

combining the first and second resultants to generate output data.

2. The method of claim 1, wherein selecting a first set of digits further includes:

masking all the digits except those in the first digit position.

3. The method of claim 2, wherein masking all the digits of the plurality of bytes except those in the first digit position further includes:

defining a first mask constant to mask the most significant digits of each byte; and

combining the first mask constant and the input data with a logical AND operation.

4. The method of claim 1, wherein selecting a second set of digits includes:

masking all the digits except those in the third digit position.

5. The method of claim 4, wherein masking all the digits of the plurality of bytes except those in the third digit position includes:

defining a second mask constant to mask the least significant digits of each byte; and

combining the second mask constant and the input data with a logical AND operation.

6. The method of claim 1, wherein shifting the digits in the first set of digits to a second digit position includes:

shifting the digits in the first set of digits by one digit to the left.

7. The method of claim 1, wherein shifting the digits in the second set of digits to a fourth digit position includes:

shifting the digits in the second set of digits by one digit to the right.

8. The method of claim 1, wherein combining the first and second resultants includes:

adding the first and second resultants.

9. The method of claim 1, wherein selecting the first set of digits and said selecting the second set of digits occur in parallel.

10. The method of claim 1, wherein receiving input data includes:

receiving an address, the address including a plurality of bytes, with each byte having a plurality of digits arranged in positions.

11. An apparatus, comprising:

a processor adapted to receive input data, the input data including a plurality of bytes, each byte having a plurality of digits arranged in positions; and

a program storage device coupled to the processor and adapted to store instructions, that when executed by the processor, perform a method, comprising;

selecting a first set of digits from the bytes having a first digit position;

shifting the digits in the first set of digits to a second digit position to generate a first resultant;

selecting a second set of digits from the bytes having a third digit position;

shifting the digits in the second set to a fourth digit position to generate a second resultant; and

combining the first and second resultants to generate output data.

12. The apparatus of claim 11, wherein selecting a first set of digits further includes masking all the digits except those in the first digit position.

13. The apparatus of claim 12, wherein masking all the digits of the plurality of bytes except those in the first digit position further includes:

defining a first mask constant to mask the most significant digits of each byte; and

combining the first mask constant and the input data with a logical AND operation.

14. The apparatus of claim 11, wherein selecting a second set of digits includes masking all the digits except those in the third digit position.

15. The apparatus of claim 14, wherein masking all the digits of the plurality of bytes except those in the third digit position includes:

defining a second mask constant to mask the least significant digits of each byte; and

combining the second mask constant and the input data with a logical AND operation.

16. The apparatus of claim 11, wherein shifting the digits in the first set of digits to a second digit position includes shifting the digits in the first set of digits by one digit to the left.

17. The apparatus of claim 11, wherein shifting the digits in the second set of digits to a fourth digit position includes shifting the digits in the second set of digits by one digit to the right.

18. The apparatus of claim 11, wherein combining the first and second resultants includes adding the first and second resultants.

19. The apparatus of claim 11, wherein selecting the first set of digits and selecting the second set of digits occur in parallel.

20. The apparatus of claim 11, wherein receiving input data includes receiving an address, the address including a plurality of bytes, with each byte having a plurality of digits arranged in positions.

21. An apparatus, comprising:

means for receiving input data, the input data including a plurality of bytes, each byte having a plurality of digits arranged in positions;

means for selecting a first set of digits from the bytes having a first digit position;

means for shifting the digits in the first set of digits to a second bit position to generate a first resultant;

means for selecting a second set of digits from the bytes having a third digit position;

means for shifting the digits in the second set of digits to a fourth digit position to generate a second resultant; and

means for combining the first and second resultants to generate output data.