Method of time multiplexing a programmable logic device

• US 6,263,430 B1
• Filed: 07/29/1999
• Issued: 07/17/2001
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wong, Jennifer, Trimberger, Stephen M., Carberry, Richard A., Johnson, Robert Anders
• Primary Examiner(s): Butler, Dennis M.
• Application Number:
  US09/363,940
• Time in Patent Office: 719 Days
• Field of Search: 713/1, 713/100, 713/400, 713/500, 713/501, 713/600
• US Class Current: 713/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Claims

1. A method of time multiplexing a programmable logic device to simulate a logic network having asynchronous clocks, the method comprising the steps of:

identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal;

re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, such that each of the one or more combinational logic elements has input signals that derive from sequential logic elements controlled by a single clock signal; and

partitioning the logic network into a plurality of sub-networks, wherein each of the sub-networks operates only in response to a single clock signal.

2. The method of claim 1, further comprising the steps of:

dividing the sub-networks into a plurality of micro-cycles; and

sequencing the micro-cycles in response to a sequencer clock.

3. The method of claim 2, further comprising the step of bypassing an idle state while sequencing the micro-cycles.

4. The method of claim 3, wherein the bypassing step comprises the step of determining a next micro-cycle to be processed while a last micro-cycle of a sequence is being processed.

5. The method of claim 1, further comprising the steps of:

dividing the sub-networks into a plurality of micro cycles; and

storing a plurality of intermediate logic states corresponding to said plurality of micro cycles, wherein each intermediate logic state is selectively accessible during each of said plurality of micro-cycles.

6. The method of claim 1, wherein the step of partitioning further comprises the steps of:

partitioning the logic network into a first sub-network that operates only in response to a first clock signal; and

partitioning the logic network into a second sub-network that operates only in response to a second clock signal, wherein the first clock signal and the second clock signal are asynchronous.

7. A method of time multiplexing a programmable logic device to simulate a logic network having asynchronous clocks, the method comprising the steps of:

identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal;

re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby creating a first set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a first clock signal, and a second set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a second clock signal, wherein the first and second clock signals are asynchronous; and

partitioning the logic network into a plurality of sub-networks, including a first sub-network that operates only in response to the first clock signal, and a second sub-network that operates only in response to the second clock signal.

8. A method of time multiplexing a programmable logic device to simulate a logic network having asynchronous clocks, the method comprising the steps of:

identifying a set of one or more combinational logic elements in the logic network, wherein at least one of the one or more combinational logic elements is coupled to receive a first input signal triggered by a first clock signal and a second input signal triggered by a second clock signal, wherein the first clock signal and the second clock signal are asynchronous;

re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby providing re-timed combinational logic elements, each being coupled to receive input signals that are triggered by either the first clock signal or the second clock signal, but not both; and

partitioning the logic network into a first sub-network that includes the re-timed combinational logic elements that are coupled to receive input signals that are triggered by a the first clock signal; and

partitioning the logic network into a second sub-network that includes the re-timed combinational logic elements that are coupled to receive input signals that are triggered by the second clock signal.