×

Method of time multiplexing a programmable logic device

  • US 6,263,430 B1
  • Filed: 07/29/1999
  • Issued: 07/17/2001
  • Est. Priority Date: 08/18/1995
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of time multiplexing a programmable logic device to simulate a logic network having asynchronous clocks, the method comprising the steps of:

  • identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal;

    re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, such that each of the one or more combinational logic elements has input signals that derive from sequential logic elements controlled by a single clock signal; and

    partitioning the logic network into a plurality of sub-networks, wherein each of the sub-networks operates only in response to a single clock signal.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×