Power control system for synchronous memory device

• US 6,263,448 B1
• Filed: 10/09/1998
• Issued: 07/17/2001
• Est. Priority Date: 10/10/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Stark, Donald C.
• Primary Examiner(s): Black, Thomas
• Assistant Examiner(s): Wang, Mary
• Application Number:
  US09/169,378
• Time in Patent Office: 1,012 Days
• Field of Search: 713/501, 713/500, 713/600, 713/300, 713/322, 713/502, 713/503, 712/219
• US Class Current: 713/501
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Claims

1. A memory system comprising;

a memory;

a memory interface coupled to the memory;

a memory bus activity monitor configured to determine a needed bandwidth of the interface;

at least a portion of one of the memory and the memory interface having at least two clock speeds; and

a clock controller configured to dynamically select a clock speed from among the at least two clock speeds in accordance with said needed bandwidth of the interface.

2. The memory system of claim 1, wherein the clock controller comprises a programmed microprocessor.

3. The memory system of claim 1, wherein one of the at least two clock speeds is a slow clock selected by the clock controller when needed bandwidth is determined by the memory bus activity monitor to be below a predefined threshold, and the slow clock speed is slower than another one of the at least two clock speeds.

4. The memory system of claim 1, wherein the at least two clock speeds includes a first clock speed and a second clock speed that is slower than the first clock speed, the clock controller selects the first clock speed when bus traffic on the memory bus exceeds a predefined threshold, and selects the second clock speed when bus traffic on the memory bus falls below the predefined threshold.

5. A memory device, comprising

a memory core;

and

a memory core interface, including RAS control circuitry and CAS control circuitry distinct from the RAS control circuitry, the RAS and CAS control circuitry coupled with said memory core;

said RAS control circuitry configured to energize said CAS control circuitry from a low power state in response to said RAS control circuitry receiving a RAS control signal and before said memory core interface receives a CAS control signal, such that said CAS control circuitry is ready to process the CAS control signal when the CAS control signal is received by said memory core interface.

6. The memory device of claim 5, wherein said CAS control circuitry is energized in a period of time less than a predefined RAS to CAS delay.

7. The memory device of claim 5, wherein upon receipt of said CAS control signal by said CAS control circuitry, said CAS control circuitry does not incur a low power state to full power state latency.

8. The memory device of claim 5, wherein the CAS control circuitry includes a receiver.

9. The memory device of claim 8, wherein the RAS control circuitry is operable to energize the receiver.

10. The memory device of claim 5, wherein the RAS control circuitry is operable to energize the CAS control circuitry by enabling a clock signal.

11. A memory device, comprising;

a memory core; and

a memory core interface, including a CAS control circuit and a write data path circuit coupled to said memory core;

said CAS control circuit configured to energize said write data path circuit from a low power state in response to said CAS control circuit receiving a CAS write control signal and before said memory core interface receives write data to be written to said memory core, such that said write data path circuit is ready to receive the write data before the write data to be written to said memory core is received.

12. The memory device of claim 11, wherein said write data path is automatically de-energized after a write data transfer is complete.

13. The memory device of claim 11, wherein the write data path circuit includes a receiver.

14. The memory device of claim 13, wherein the CAS control circuit is operable to energize the receiver.

15. The memory device of claim 11, wherein the write data path circuit includes a write input pipeline.

16. The memory device of claim 11, wherein the CAS control circuit is operable to energize the write data path circuit by enabling a clock signal.

17. A memory device, comprising:

a memory core; and

a memory interface, including a CAS control circuit and a read data path circuit, the CAS control circuit coupled to a control bus and the read data path circuit coupled to a database and said memory core;

said CAS control circuit configured to energize said read data path circuit from a low power state in response to said CAS control circuit receiving a CAS read control signal and before said memory interface receives read data from said memory core, such that said read data path circuit is ready to receive the read data before the read data from said memory core is available.

18. The memory device of claim 17, wherein said read data path is automatically de-energized after a read data transfer is complete.

19. The memory device of claim 17, wherein the read data path circuit includes a read output pipeline.

20. The memory device of claim 17, wherein the CAS control circuit is operable to energize the read data path circuit by enabling a clock signal.

21. A memory device comprising:

a memory core;

a first pipeline stage coupled to said memory core; and

a second pipeline stage coupled to said memory core, said second pipeline stage having an associated power-up latency comprising a period of time required to energize said second pipeline stage to a ready state from a low power state; and

said first pipeline stage configured to energize said second pipeline stage from said low power state, before said second pipeline stage receives a second signal, in response to said first pipeline stage receiving a first signal, such that said second pipeline stage is ready to process said second signal when said second signal is received by said second pipeline stage without incurring said power-up latency.

22. The memory device of claim 21, wherein said first pipeline circuit is selected from a group consisting of:

RAS control circuitry; and

CAS control circuitry.

23. The memory device of claim 21, wherein said second pipeline circuit is selected from a group consisting of:

CAS control circuitry

read data path circuitry; and

write data path circuitry.

24. The memory device of claim 21, further comprising:

a clock source for providing a slow clock signal and a fast clock signal; and

a clock controller configured to dynamically select one of the slow clock signal and fast clock signal for output to the first and second pipeline stages in accordance with a needed bandwidth.

25. The memory device of claim 24, wherein said clock source derives the slow clock signal from the fast clock signal.

26. The memory device of claim 24, wherein said clock controller is configured to compare said needed bandwidth with a predefined threshold and to perform the dynamic selection in accordance therewith.

27. The memory device of claim 26, wherein said clock controller monitors bus traffic on a memory bus to determine the needed bandwidth.

31. The memory device of claim 25, wherein said first pipeline stage includes a close operation control circuit that automatically deactivates said second pipeline stage.

28. A synchronous memory device comprising:

a memory core;

a first pipeline stage coupled to said memory core;

a second pipeline stage coupled to said memory core;

a synchronous clock source for providing a clock signal synchronized to an externally provided clock signal; and

synchronous logic, coupled to said first pipeline stage, said second pipeline stage and said clock source, for supplying of said first pipeline stage and prior to the second pipeline stage receiving a signal to process.

29. The memory device of claim 28, wherein

said second pipeline stage has an associated power-up latency comprising a period of time required to energize said second pipeline stage to a ready state from a low power state; and

the synchronous logic supplies the clock signal to the second pipeline stage such that the second pipeline stage is ready to process the signal when the signal is received by the second pipeline stage without incurring said power-up latency.

30. The memory device of claim 28, wherein said first pipeline stage includes a sense control circuit, said first pipeline stage automatically activating said second pipeline stage, the second pipeline stage including transfer and close control circuits.

32. A memory system, for use in conjunction with a memory bus activity monitor, comprising:

a memory;

a memory interface coupled to the memory;

at least a portion of one of the memory and the memory interface having at least two clock speeds; and

a clock controller configured to dynamically select a clock speed from among the at least two clock speeds in accordance with a needed bandwidth of the interface, the needed bandwidth of the interface based on measurements made by a memory bus activity monitor.

33. The memory system of claim 32, wherein the clock controller comprises a programed microprocessor.

34. The memory system of claim 32, wherein one of the at least two clock speeds is a slow clock selected by the clock controller when needed bandwidth is determined by a memory bus activity monitor to be below a predefined threshold, and the slow clock speed is slower than another one of the at least two clock speeds.

35. The memory system of claim 32, wherein the at least two clock speeds includes a first clock speed and a second clock speed that is slower than the first clock speed, the clock controller selects the first clock speed when bus traffic on the memory bus exceeds a predefined threshold, and selects the second clock speed when bus traffic on the memory bus falls below the predefined threshold.