Power control system for synchronous memory device
First Claim
1. A memory system comprising;
- a memory;
a memory interface coupled to the memory;
a memory bus activity monitor configured to determine a needed bandwidth of the interface;
at least a portion of one of the memory and the memory interface having at least two clock speeds; and
a clock controller configured to dynamically select a clock speed from among the at least two clock speeds in accordance with said needed bandwidth of the interface.
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Accused Products
Abstract
A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.
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Citations
35 Claims
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1. A memory system comprising;
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a memory;
a memory interface coupled to the memory;
a memory bus activity monitor configured to determine a needed bandwidth of the interface;
at least a portion of one of the memory and the memory interface having at least two clock speeds; and
a clock controller configured to dynamically select a clock speed from among the at least two clock speeds in accordance with said needed bandwidth of the interface. - View Dependent Claims (2, 3, 4)
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5. A memory device, comprising
a memory core; - and
a memory core interface, including RAS control circuitry and CAS control circuitry distinct from the RAS control circuitry, the RAS and CAS control circuitry coupled with said memory core;
said RAS control circuitry configured to energize said CAS control circuitry from a low power state in response to said RAS control circuitry receiving a RAS control signal and before said memory core interface receives a CAS control signal, such that said CAS control circuitry is ready to process the CAS control signal when the CAS control signal is received by said memory core interface. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A memory device, comprising;
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a memory core; and
a memory core interface, including a CAS control circuit and a write data path circuit coupled to said memory core;
said CAS control circuit configured to energize said write data path circuit from a low power state in response to said CAS control circuit receiving a CAS write control signal and before said memory core interface receives write data to be written to said memory core, such that said write data path circuit is ready to receive the write data before the write data to be written to said memory core is received. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory device, comprising:
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a memory core; and
a memory interface, including a CAS control circuit and a read data path circuit, the CAS control circuit coupled to a control bus and the read data path circuit coupled to a database and said memory core;
said CAS control circuit configured to energize said read data path circuit from a low power state in response to said CAS control circuit receiving a CAS read control signal and before said memory interface receives read data from said memory core, such that said read data path circuit is ready to receive the read data before the read data from said memory core is available. - View Dependent Claims (18, 19, 20)
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21. A memory device comprising:
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a memory core;
a first pipeline stage coupled to said memory core; and
a second pipeline stage coupled to said memory core, said second pipeline stage having an associated power-up latency comprising a period of time required to energize said second pipeline stage to a ready state from a low power state; and
said first pipeline stage configured to energize said second pipeline stage from said low power state, before said second pipeline stage receives a second signal, in response to said first pipeline stage receiving a first signal, such that said second pipeline stage is ready to process said second signal when said second signal is received by said second pipeline stage without incurring said power-up latency. - View Dependent Claims (22, 23, 24, 25, 26, 27, 31)
RAS control circuitry; and
CAS control circuitry.
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23. The memory device of claim 21, wherein said second pipeline circuit is selected from a group consisting of:
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CAS control circuitry read data path circuitry; and
write data path circuitry.
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24. The memory device of claim 21, further comprising:
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a clock source for providing a slow clock signal and a fast clock signal; and
a clock controller configured to dynamically select one of the slow clock signal and fast clock signal for output to the first and second pipeline stages in accordance with a needed bandwidth.
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25. The memory device of claim 24, wherein said clock source derives the slow clock signal from the fast clock signal.
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26. The memory device of claim 24, wherein said clock controller is configured to compare said needed bandwidth with a predefined threshold and to perform the dynamic selection in accordance therewith.
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27. The memory device of claim 26, wherein said clock controller monitors bus traffic on a memory bus to determine the needed bandwidth.
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31. The memory device of claim 25, wherein said first pipeline stage includes a close operation control circuit that automatically deactivates said second pipeline stage.
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28. A synchronous memory device comprising:
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a memory core;
a first pipeline stage coupled to said memory core;
a second pipeline stage coupled to said memory core;
a synchronous clock source for providing a clock signal synchronized to an externally provided clock signal; and
synchronous logic, coupled to said first pipeline stage, said second pipeline stage and said clock source, for supplying of said first pipeline stage and prior to the second pipeline stage receiving a signal to process. - View Dependent Claims (29, 30)
said second pipeline stage has an associated power-up latency comprising a period of time required to energize said second pipeline stage to a ready state from a low power state; - and
the synchronous logic supplies the clock signal to the second pipeline stage such that the second pipeline stage is ready to process the signal when the signal is received by the second pipeline stage without incurring said power-up latency.
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30. The memory device of claim 28, wherein said first pipeline stage includes a sense control circuit, said first pipeline stage automatically activating said second pipeline stage, the second pipeline stage including transfer and close control circuits.
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32. A memory system, for use in conjunction with a memory bus activity monitor, comprising:
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a memory;
a memory interface coupled to the memory;
at least a portion of one of the memory and the memory interface having at least two clock speeds; and
a clock controller configured to dynamically select a clock speed from among the at least two clock speeds in accordance with a needed bandwidth of the interface, the needed bandwidth of the interface based on measurements made by a memory bus activity monitor. - View Dependent Claims (33, 34, 35)
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Specification