Yield based, in-line defect sampling method

• US 6,265,232 B1
• Filed: 08/21/1998
• Issued: 07/24/2001
• Est. Priority Date: 08/21/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Simmons, Steven J.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/138,295
• Time in Patent Office: 1,068 Days
• Field of Search: 438/14, 438/4, 438/7
• US Class Current: 438/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (IC'"'"'s). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Claims

1. A method for processing integrated circuit semiconductor dice on a wafer in a manufacturing process for said dice, said method comprising:

inspecting said integrated circuit semiconductor dice on said wafer to determine defects thereon and classifying each of said defects by size and location, said inspecting and classifying comprising classifying said each of said defects into one of size range populations of defects;

assigning a weight to said each of said defects representing an estimated effect of said each of said defects on die yield for said integrated circuit semiconductor dice;

determining an estimated die yield loss (DYL) for each die of said integrated circuit semiconductor dice based on number and weight of said defect(s) on each said die;

summing all DYL of said integrated circuit semiconductor dice on said wafer to obtain a wafer yield loss (WYL);

subdividing the defects into a plurality of size range populations of defects for said integrated circuit semiconductor dice; and

determining a relative contribution of each size range population of defects of said plurality for said integrated circuit semiconductor dice to wafer yield loss WYL.

2. The method of claim 1, wherein said determining said estimated die yield loss comprises calculating an estimated die yield loss having lower and upper limits of zero and 1.0, respectively.

3. The method of claim 2, wherein said lower limit comprises a representation of no yield loss attributable to said defects and said upper limit comprises a representation of fatal yield loss attributable to said defect.

4. The method of claim 1, wherein said determining said estimated die yield loss (DYL) comprises calculating an estimated die yield loss having a lower limit and an upper limit of zero and 1.0, respectively.

5. The method of claim 1, wherein said subdividing said defects into said plurality of size range populations of defects comprises subdividing side defects into a plurality of 0 to 10 size range populations.

7. The method of claim 1, further comprising:

randomly selecting defects from said each size range population of defects of said plurality, a number selected from said each size range population of defects of said plurality in proportion to said relative contribution thereof, whereby said randomly selected defects are weighted to represent defects having greatest effect on yield losses.

8. The method of claim 7, further comprising:

reviewing said randomly selected defects and determining in-line action required to reduce wafer yield losses.

9. The method of claim 8, wherein said reviewing said randomly selected defects includes visual inspection by one of a scanning microscope and an optical microscope.

10. The method of claim 9, wherein said determining in-line action comprises determining if an individual die on said wafer is acceptable to proceed in said manufacturing process.

11. The method of claim 1, wherein said inspecting said dice is performed by an automated surface inspection tool.

6. A method for processing integrated circuit semiconductor dice on a wafer in a manufacturing process for said dice, said method comprising:

inspecting said integrated circuit semiconductor dice on said wafer to determine defects thereon and classifying each of said defects by size and location, said inspecting and classifying comprising classifying said each of said defects into one of size range populations of defects;

assigning a weight to said each of said defects representing an estimated effect of said defects on die yield for said integrated circuit semiconductor dice;

determining an estimated die yield loss (DYL) for each die of said integrated circuit semiconductor dice based on number and weight of said defect(s) on said each die;

summing all DYL of said integrated circuit semiconductor dice on said wafer to obtain a wafer yield loss (WYL);

subdividing the defects into a plurality of size range populations of defects; and

determining a relative contribution of each size range population of defects of said plurality to wafer yield loss WYL, said determining the relative contribution of said each size range population of defects of said plurality to wafer yield loss comprises;

discarding data for said each size range population of defects of said plurality and calculating, in turn, a drop in wafer yield loss for combined size range populations excepting the discarded data;

summing the calculated wafer yield losses to obtain a drop sum; and

dividing said drop sum to determine a relative drop attributable to said each size range population of defects of said plurality.

12. A method for processing integrated circuit semiconductor dice on a wafer in a manufacturing process for said dice, said method comprising:

inspecting on said wafer to determine defects thereon and classifying each of said defects by size and location;

assigning a weight to said each of said defects representing an estimated effect of said each of said defects on die yield;

determining an estimated die yield loss (DYL) for each die based on number and weight of said defect(s) on said each said die of said integrated circuit semiconductor dice;

summing all DYL of said integrated circuit semiconductor dice on said wafer to obtain a wafer yield loss (WYL);

subdividing the defects into a plurality of size range populations of defects;

determining a relative contribution of each size range population of defects of said plurality to wafer yield loss WYL; and

randomly selecting defects from said each size range population of defects of the plurality, a number selected from said each size range population of defects of the plurality in proportion to said relative contribution thereof, said randomly selected defects weighted to represent defects having greatest effect on yield losses.

13. The method of claim 12, further comprising:

reviewing said randomly selected defects and determining in-line action required to reduce wafer yield losses.

14. The method of claim 12, wherein said inspecting said dice and classifying said defects comprises classifying each of said defects into one of said plurality of size range populations of defects.

15. The method of claim 12, wherein said determining said estimated die yield loss comprises calculating an estimated die yield loss having lower and upper limits of zero and 1.0, respectively.

16. The method of claim 15, wherein said lower limit comprises a representation of no yield loss attributable to said defects and said upper limit comprises a representation of fatal yield loss attributable to said defects.

17. The method of claim 12, wherein said subdividing said defects into said plurality of size range populations of defects comprises subdividing said defects into a plurality of 0 to 10 size range populations.

18. The method of claim 12, wherein said determining the relative contribution of said each size range population of defects of said plurality to wafer yield loss comprises:

discarding data for said each size range population of defects of said plurality and calculating, in turn, a drop in wafer yield loss for combined size range populations excepting the discarded data;

summing the calculated drop in wafer yield losses to obtain a drop sum; and

dividing said drop sum to determine a relative drop attributable to said each size range population of defects of said plurality.

19. The method of claim 13, wherein said reviewing said randomly selected defects includes visual inspection by one of a scanning microscope and an optical microscope.

20. The method of claim 13, wherein said determining in-line action required to reduce wafer yield losses comprises determining if an individual die on said wafer is acceptable to proceed in said manufacturing process.

21. The method of claim 12, wherein said inspecting said dice is performed by an automated surface inspection tool.

22. A method for processing integrated circuit semiconductor dice on a wafer in a manufacturing process for said dice, said method comprising:

inspecting said dice on said wafer to determine defects thereon and classifying each of said defects by size and location, said inspecting and classifying comprises classifying said each of said defects into one of size range populations of defects;

assigning a weight to said each of said defects representing an estimated effect of said each of said defects on die yield;

determining an estimated die yield loss (DYL) for each die based on number and weight of said defect(s) on said each die of said integrated circuit semiconductor dice;

summing all DYL of said integrated circuit semiconductor dice on said wafer to obtain a wafer yield loss (WYL);

subdividing the defects into a plurality of size range populations of defects;

determining a relative contribution of each size range population of defects of said plurality to wafer yield loss WYL;

randomly selecting defects from each size range population of defects of the plurality, a number selected from said each size range population of defects of the plurality in proportion to said relative contribution thereof, said randomly selected defects weighted to represent defects having greatest effect on yield losses; and

reviewing said randomly selected defects and determining in-line action required to reduce wafer yield losses.

23. The method of claim 22, wherein said determining said estimated die yield loss comprises calculating an estimated die yield loss having lower and upper limits of zero and 1.0, respectively.

24. The method of claim 23, wherein said lower limit comprises a representation of no yield loss attributable to said defects and said upper limit comprises a representation of fatal yield loss attributable to said defects.

25. The method of claim 22, wherein said subdividing said defects into said plurality of size range populations of defects comprises subdividing said defects into a plurality of 0 to 10 size range populations.

26. The method of claim 22, wherein said determining the relative contribution of said each size range population of defects of said plurality to wafer yield loss comprises:

discarding data for said each size range population of defects of said plurality and calculating, in turn, a drop in wafer yield loss for combined size range populations excepting the discarded data;

summing the calculated drop in wafer yield losses to obtain a drop sum; and

dividing said drop sum to determine a relative drop sum attributable to said each size range population of defects of said plurality.

27. The method of claim 23, wherein said reviewing said randomly selected defects includes visual inspection by one of a scanning microscope and an optical microscope.

28. The method of claim 23, wherein said determining in-line action comprises determining if an individual die on said wafer is acceptable to proceed in said manufacturing process.

29. The method of claim 28, wherein said inspecting said dice is performed by an automated surface inspection tool.