Semiconductor integrated circuit devices and a method of manufacturing the same

• US 6,265,254 B1
• Filed: 12/30/1999
• Issued: 07/24/2001
• Est. Priority Date: 12/13/1996
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Asakura, Hisao
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US09/475,048
• Time in Patent Office: 572 Days
• Field of Search: 438/197, 438/199, 438/200, 438/237, 438/232
• US Class Current: 438/199
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

Claims

1. A method of manufacturing a semiconductor integrated circuit device having an n-channel MIS transistor formed at a first portion and a first conductor layer at a second portion in a p-well region and

a p-channel MIS transistor formed at a first portion and a second conductor layer at a second portion in an n-well region, comprising the steps of:

(a) forming the p-well region and the n-well region in a semiconductor substrate;

(b) forming a first mask covering the first portion in the n-well region and exposing the first portion in the p-well region and the second portion in the n-well region;

(c) implanting n-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form n-type impurity implanted regions;

(d) implanting p-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form p-type impurity implanted regions; and

(e) forming a second conductor layer at the second portion in the n-well region;

wherein the n-type impurity implanted regions are implanted deeper than the p-type impurity implanted region, and wherein the second conductor layer electrically connects with the n-type impurity implanted region in the n-type well region.

2. A method of manufacturing a semiconductor integrated circuit device having an n-channel MIS transistor formed at a first portion and a first conductor layer at a second portion in a p-well region and

a p-channel MIS transistor formed at a first portion and a second conductor layer at a second portion in an n-well region, comprising the steps of:

(a) forming the p-well region and n-well region in a semiconductor substrate;

(b) forming a first mask covering the first portion in the p-well region and exposing the first portion in the n-well region and the second portion in the p-well region;

(c) implanting n-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form n-type impurity implanted regions;

(d) implanting p-type impurity into the p-well region and the n-well region at a portion exposed from the first mask to form p-type impurity implanted regions; and

(e) forming a second conductor layer at the second portion in the p-well region;

wherein the p-type impurity implanted regions are implanted deeper than the n-type impurity implanted region, and the first conductor layer electrically connects with the p-type impurity implanted region in the p-type well region.